Search Results - "Toifl, T"

A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth by Kossel, M., Menolfi, C., Weiss, J., Buchmann, P., von Bueren, G., Rodoni, L., Morf, T., Toifl, T., Schmatz, M.

“…A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates…”
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A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology by Toifl, T., Menolfi, C., Ruegg, M., Reutemann, R., Buchmann, P., Kossel, M., Morf, T., Weiss, J., Schmatz, M.L.

“…We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate…”
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LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS by Kossel, M., Morf, T., Weiss, J., Buchmann, P., Menolfi, C., Toifl, T., Schmatz, M.L.

“…A wideband LC PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range. The wideband operation is…”
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30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology by Ellinger, F., Rodoni, L.C., Sialm, G., Kromer, C., von Buren, G., Schmatz, M.L., Menolfi, C., Toifl, T., Morf, T., Kossel, M., Jackel, H.

“…In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is…”
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Low-complexity adaptive equalization for high-speed chip-to-chip communication paths by zero-forcing of jitter components by Toifl, T., Schmatz, M., Menolfi, C.

“…In this letter, we show how a prefilter can be automatically adapted to open the data eye in a nonreturn to zero transmission system using only two binary…”
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A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS by Toifl, T., Menolfi, C., Buchmann, P., Kossel, M., Morf, T., Schmatz, M.L.

“…A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was…”
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Switched Inductor With Wide Tuning Range and Small Inductance Step Sizes by Kossel, M., Morf, T., Buchmann, P., Schmatz, M.L., Menolfi, C., Toifl, T.

“…A switched inductor based on mutual-inductance switching is proposed that aims at increasing the inductance tuning range as well as the number of inductance…”
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Integrated circuits for particle physics experiments by Snoeys, W., Anelli, G., Campbell, M., Cantatore, E., Faccio, F., Heijne, E.H.M., Jarron, P., Kloukinas, K.C., Marchioro, A., Moreira, P., Toifl, T., Wyllie, K.

“…High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons,…”
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4-channel rad-hard delay generation ASIC with 1 ns timing resolution for LHC by Toifl, T., Vari, R., Moreira, P., Marchioro, A.

“…An ASIC was developed to precisely delay digital signals within the range of 0-24 ns in steps of 1 ns. To obtain well defined delay values independent of…”
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A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology by Bulzacchelli, J. F., Menolfi, C., Beukema, T. J., Storaska, D. W., Hertle, J., Hanson, D. R., Ping-Hsuan Hsieh, Rylov, S. V., Furrer, D., Gardellini, D., Prati, A., Morf, T., Sharma, V., Kelkar, R., Ainspan, H. A., Kelly, W. R., Chieco, L. R., Ritter, G. A., Sorice, J. A., Garlett, J. D., Callan, R., Brandli, M., Buchmann, P., Kossel, M., Toifl, T., Friedman, D. J.

“…This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes…”
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A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS by Cevrero, A., Aprile, C., Francese, P. A., Bapst, U., Menolfi, C., Braendli, M., Kossel, M., Morf, T., Kull, L., Yueksel, H., Oezkaya, I., Leblebici, Y., Cevher, V., Toifl, T.

“…This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a…”
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A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS by Toifl, T., Menolfi, C., Ruegg, M., Reutemann, R., Dreps, D., Beukema, T., Prati, A., Gardellini, D., Kossel, M., Buchmann, P., Brandli, M., Francese, P. A., Morf, T.

“…A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the…”
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Room-temperature THz imaging based on antenna-coupled MOSFET bolometer by Morf, T., Klein, B., Despont, M., Drechsler, U., Kull, L., Corcos, D., Elad, D., Kaminski, N., Braendli, M., Menolfi, C., Kossel, M., Francese, P. A., Toifl, T., Plettemeier, D.

“…We report on the design, fabrication and measurements of a new THz sensor concept based on an antenna-coupled MOSFET bolometer for room-temperature passive THz…”
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A multiphase PLL for 10 Gb/s links in SOI CMOS technology by Kossel, M., Morf, T., Baumberger, W., Biber, A., Menolfi, C., Toifl, T., Schmatz, M.

“…This paper presents a multiphase PLL designed for a 10/spl times/10 Gbit/s serial link bundle that is based on a digital CDR receiver. The PLL was fabricated…”
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A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS by Kull, L., Toifl, T., Schmatz, M., Francese, P. A., Menolfi, C., Braendli, M., Kossel, M., Morf, T., Andersen, T. M., Leblebici, Y.

“…Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs…”
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@@iLC@ PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS by Kossel, M, Morf, T, Weiss, J, Buchmann, P, Menolfi, C, Toifl, T, Schmatz, M L

“…A wideband @@iLC@ PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range. The wideband operation is…”
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A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology by Bulzacchelli, J., Beukema, T., Storaska, D., Hsieh, P., Rylov, S., Furrer, D., Gardellini, D., Prati, A., Menolfi, C., Hanson, D., Hertle, J., Morf, T., Sharma, V., Kelkar, R., Ainspan, H., Kelly, W., Ritter, G., Garlett, J., Callan, R., Toifl, T., Friedman, D.

“…As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to…”
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A 28Gb/s source-series terminated TX in 32nm CMOS SOI by Menolfi, C., Hertle, J., Toifl, T., Morf, T., Gardellini, D., Braendli, M., Buchmann, P., Kossel, M.

“…Upcoming standards such as OIF CEI-25LR and CEI-28SR demand transmitter circuits above 20Gb/s [1]-[3] with stringent jitter requirements. The SST driver…”
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A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI by Menolfi, C, Toifl, T, Rueegg, M, Braendli, M, Buchmann, P, Kossel, M, Morf, T

“…The limited supply voltage of today's state-of-the-art CMOS technologies makes the design of high-speed transmitters at signaling swings above the typical 1 V…”
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A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS by Inti, R, Elshazly, A, Young, B, Wenjing Yin, Kossel, M, Toifl, T, Hanumolu, P K

“…Ever-growing demand for higher communication bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial…”
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