Search Results - "Tihhomirov, Valentin"

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits by Jenihhin, Maksim, Squillero, Giovanni, Copetti, Thiago Santos, Tihhomirov, Valentin, Kostin, Sergei, Gaudesi, Marco, Vargas, Fabian, Raik, Jaan, Sonza Reorda, Matteo, Bolzani Poehls, Leticia, Ubar, Raimund, Medeiros, Guilherme Cardoso

“…The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the…”
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Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs by Pellerey, Francesco, Jenihhin, Maksim, Squillero, Giovanni, Raik, Jaan, Reorda, Matteo Sonza, Tihhomirov, Valentin, Ubar, Raimund

“…The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits…”
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Assessment of diagnostic test for automated bug localization by Tihhomirov, Valentin, Tsepurov, Anton, Jenihhin, Maksim, Raik, Jaan, Ubar, Raimund

“…Statistical simulation based design error debug approaches strongly rely on quality of the diagnostic test. At the same time there exists no dedicated…”
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PSL assertion checkers synthesis with ASM based HLS tool ABELITE by Jenihhin, Maksim, Baranov, Samary, Raik, Jaan, Tihhomirov, Valentin

“…This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach…”
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A scalable model based RTL framework zamiaCAD for static analysis by Tsepurov, Anton, Bartsch, Gunter, Dorsch, Rainer, Jenihhin, Maksim, Raik, Jaan, Tihhomirov, Valentin

“…As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous…”
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Localization of Bugs in Processor Designs Using zamiaCAD Framework by Tepurov, Anton, Tihhomirov, Valentin, Jenihhin, Maksim, Raik, Jaan, Bartsch, Gunter, Escobar, Jorge Hernan Meza, Wuttke, Heinz-Dietrich

“…This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically…”
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Improved fault emulation for synchronous sequential circuits by Raik, J., Ellervee, P., Tihhomirov, V., Ubar, R.

“…Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation…”
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FPGA based fault emulation of synchronous sequential circuits by Ellervee, P., Raik, J., Tihhomirov, V., Ubar, R.

“…This paper describes a feasibility study of accelerating fault simulation by emulation on FPGA. Fault simulation b an important subtask in test pattern…”
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Automated Design Error Localization in RTL Designs by Jenihhin, Maksim, Tsepurov, Anton, Tihhomirov, Valentin, Raik, Jaan, Hantson, Hanno, Ubar, Raimund, Bartsch, Gunter, Escobar, JorgeHernan Meza, Wuttke, Heinz-Dietrich

“…This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification…”
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