Search Results - "Tien-Sheng Chao"

CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications by Kuo, Yi-Shan, Lee, Shen-Yang, Lee, Chia-Chin, Li, Shou-Wei, Chao, Tien-Sheng

“…A low-cost fabrication process of Hf 1-x Zr x O 2 (HZO) nonvolatile memory (NVM) was proposed and its characteristics were investigated. We successfully…”
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Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability by Lin, Jer-Yi, Kumar, Malkundi Puttaveerappa Vijay, Chao, Tien-Sheng

“…In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature…”
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Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters by Sung, Po-Jung, Chang, Shu-Wei, Kao, Kuo-Hsing, Wu, Chien-Ting, Su, Chun-Jung, Cho, Ta-Chun, Hsueh, Fu-Kuo, Lee, Wen-Hsi, Lee, Yao-Jen, Chao, Tien-Sheng

“…In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were…”
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Reliability of p-Type Pi-Gate Poly-Si Nanowire Channel Junctionless Accumulation-Mode FETs by Hsieh, Dong-Ru, Lin, Kun-Cheng, Lee, Chia-Chin, Chao, Tien-Sheng

“…In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated…”
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Fabrication of GeSn Nanowire MOSFETs by Utilizing Highly Selective Etching Techniques by Hong, Tzu-Chieh, Lu, Wen-Hsiang, Wang, Yeong-Her, Li, Jiun-Yun, Lee, Yao-Jen, Chao, Tien-Sheng

“…Germanium-tin (GeSn) epitaxy layer was prepared on an 8-in SOI wafer with a Ge buffer layer. The etching rates of different solutions for the GeSn layer were…”
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Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels by Su, Chun-Jung, Tsai, Tzu-I, Liou, Yu-Ling, Lin, Zer-Ming, Lin, Horng-Chih, Chao, Tien-Sheng

“…In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire…”
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Single‐Gate In‐Transistor Readout of Current Superposition and Collapse Utilizing Quantum Tunneling and Ferroelectric Switching by Chen, Ching‐Hung, Lai, Yu‐Ting, Chen, Ciao‐Fen, Wu, Pei‐Tzu, Su, Kuan‐Jung, Hsu, Sheng‐Yang, Dai, Guo‐Jin, Huang, Zan‐Yi, Hsu, Chien‐Lung, Lee, Shen‐Yang, Shen, Chuan‐Hui, Chen, Hsin‐Yu, Lee, Chia‐Chin, Hsieh, Dong‐Ru, Lin, Yen‐Fu, Chao, Tien‐Sheng, Lo, Shun‐Tsung

“…In nanostructure assemblies, the superposition of current paths forms microscopic electric circuits, and different circuit networks produce varying results,…”
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Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs by Hsieh, Dong-Ru, Lin, Jer-Yi, Kuo, Po-Yi, Chao, Tien-Sheng

“…In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n + doped poly-Si (DP-Si) fin-channels have been…”
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Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs by Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng

“…In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and…”
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High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET by Hsieh, Dong-Ru, Lin, Jer-Yi, Kuo, Po-Yi, Chao, Tien-Sheng

“…In this paper, the Pi-gate (PG) poly-Si junction-less (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4)…”
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Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs by Kumar, Malkundi Puttaveerappa Vijay, Chia-Ying Hu, Kuo-Hsing Kao, Yao-Jen Lee, Tien-Sheng Chao

“…This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current,…”
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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application by Lin, Jer-Yi, Kuo, Po-Yi, Lin, Ko-Li, Chin, Chun-Chieh, Chao, Tien-Sheng

“…In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised…”
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Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process by Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng

“…For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si…”
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Investigation of Two Bits With Multistate Antifuse on nMOS Poly-Silicon Junctionless GAA OTP by Chang, Chen-Feng, Shen, Chiuan-Huei, Hsieh, Dong-Ru, Lu, Zong-Han, Lin, Cheng-Chen, Chao, Tien-Sheng

“…One-time programmable (OTP) memory is essential to the security and gaming industries because of its "write once, read many" capability. This device supports…”
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Highly Stable Short Channel Ultrathin Atomic Layer Deposited Indium Zinc Oxide Thin Film Transistors With Excellent Electrical Characteristics by Liang, Yan-Kui, Li, Wei-Li, Zheng, Jun-Yang, Lin, Yu-Lon, Lu, Yu-Cheng, Chiu, Ching-Hua, Hsieh, Dong-Ru, Chou, Tsung-Te, Kei, Chi-Chung, Huang, Huai-Ying, Lin, Yu-Ming, Tseng, Yuan-Chieh, Chao, Tien-Sheng, Chang, Edward Yi, Lin, Chun-Hsiung

“…The high-performance atomic layer deposited (ALD) ultrathin (~2 nm) amorphous InZnO (<inline-formula> <tex-math notation="LaTeX">{a}…”
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Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing by Chung, Sheng-Ti, Lee, Yao-Jen, Chao, Tien-Sheng

“…In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing…”
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High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n+-Doped Poly-Si NWs Channels Junctionless FETs by Kuo, Po-Yi, Lu, Yi-Hsien, Chao, Tien-Sheng

“…The gate-all-around sidewall-damascened sub10-nm in situ n + -doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm 2…”
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Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization by Kumar, Malkundi Puttaveerappa Vijay, Chia-Ying Hu, Walke, Amey Mahadev, Kuo-Hsing Kao, Tien-Sheng Chao

“…This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical…”
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A Harmonic Radar Tag with High Detection Range Utilizing Ge FinFETs CMOS Technology by Hsieh, Cheng-Hung, Hong, Tzu-Chieh, Yang, Chiung-Yi, Chen, Yi-Ho, Yu, Xin-Ren, Lu, Wen-Hsiang, Chuang, Ricky W., Tsai, Zuo-Min, Lee, Yao-Jen, Li, YiMing, Wu, Wen-Fa, Chao, Tien-Sheng, Samukawa, Seiji, Wang, Yeong-Her, Yeh, Wen-Kuan, Tarng, Jenn-Hwan

“…This study fabricated and verified a germanium (Ge) fin field-effect transistor (FinFET) on developed GeSOI platform. The Ge FinFETs were demonstrated for…”
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Low-Temperature Microwave Annealing Processes for Future IC Fabrication-A Review by Lee, Yao-Jen, Cho, Ta-Chun, Chuang, Shang-Shiun, Hsueh, Fu-Kuo, Lu, Yu-Lun, Sung, Po-Jung, Chen, Hsiu-Chih, Current, Michael I., Tseng, Tseung-Yuen, Chao, Tien-Sheng, Hu, Chenming, Yang, Fu-Liang

“…Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly…”
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