Search Results - "Tien-Chien Kuo"
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A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate
Published in IEEE journal of solid-state circuits (01-01-2009)“…A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3)…”
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Journal Article Conference Proceeding -
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A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01-02-2008)“…We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added…”
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Conference Proceeding -
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Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology
Published in IEEE transactions on very large scale integration (VLSI) systems (01-06-1997)“…This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs Heterojunction MESFET (HMESFET) processor…”
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Journal Article