Search Results - "Thuries, S."

A comprehensive study of Monolithic 3D cell on cell design using commercial 2D tool by Billoint, O., Sarhan, H., Rayane, I., Vinet, M., Batude, P., Fenouillet-Beranger, C., Rozeau, O., Cibrario, G., Deprat, F., Fustier, A., Michallet, J-E, Faynot, O., Turkyilmaz, O., Christmann, J-F, Thuries, S., Clermidy, F.

“…In this paper we present a methodology allowing an emulated-3D two tiers physical implementation of any design using 2D commercial tools. Place and Route is…”
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Mm-wave automotive radar: from evolution to revolution by Doris, K., Jansen, F., Lont, M., Dinh, T.V., Syed, W., Carluccio, G., Tiemeijer, L. F., Saric, T., Zong, Z., Osorio, J., Janssen, E., Thuries, S., Ganzerli, M., Filippi, A., Graauw, A. d., Salle, D., Vaucher, C.S.

“…This paper describes the evolving landscape of 76-81 GHz automotive radar at technology, circuit, and waveform level and shows the opportunities and challenges…”
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Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations by Billoint, O., Azizi-Mourier, K., Cibrario, G., Lattard, D., Mouhdach, M., Thuries, S., Vivet, P.

“…Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed…”
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Opportunities and challenges brought by 3D-sequential integration by Batude, P., Brunet, L., Fenouillet-Beranger, C., Lattard, D., Andrieu, F., Vinet, M., Brevard, L., Ribotta, M., Previtali, B., Tabone, C., Ponthenier, F., Rambal, N., Sideris, P., Garros, X., Casse, M., Theodorou, C., Sklenard, B., Lacord, J., Besson, P., Fournel, F., Kerdiles, S., Acosta-Alba, P., Mazzocchi, V., Hartmann, J-M., Mazen, F., Thuries, S., Billoint, O., Vivet, P., Sicard, G., Cibrario, G., Mouhdach, M., Giraud, B., Ribotta, CM, Lapras, V.

“…The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view…”
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3D sequential integration: applications and associated key enabling modules (design & technology) by Batude, P., Billoint, O., Thuries, S., Malinge, P., Fenouillet-Beranger, C., Peizerat, A., Sicard, G., Vivet, P., Reboh, S., Cavalcante, C., Brunet, L., Ribotta, M., Brevard, L., Garros, X., Frutuoso, T. Mota, Sklenard, B., Lacord, J., Kanyandekwe, J., Kerdiles, S., Sideris, P., Theodorou, C., Lapras, V., Mouhdach, M., Gaudin, G., Besnard, G., Radu, I., Ponthenier, F., Farcy, A., Jesse, E., Guyader, F., Matheret, T., Brunet, P., Milesi, F., Van-Jodin, L. Le, Sarrazin, A., Perrin, B., Moulin, C., Maitrejean, S., Alepidis, M., Ionica, I., Cristoloveanu, S., Gaillard, F., Vinet, M., Andrieu, F., Arcamone, J., Ollier, E.

“…3D sequential integration (3DSI) is envisioned for highly miniaturized smart imagers and fine pitch logic and memory imbrication. This paper describes…”
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New perspectives for multicore architectures using advanced technologies by Clermidy, F., Vivet, P., Dutoit, D., Thonnart, Y., Gonzales, J. L., Noel, J. P., Giraud, B., Levisse, A., Billoint, O., Thuries, S.

“…Impact of advanced technologies on the design and structure of multicore architectures is presented in this paper. More specifically, the power consumption and…”
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Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation by Andrieu, F., Berthelon, R., Boumchedda, R., Tricaud, G., Brunet, L., Batude, P., Mathieu, B., Avelar, E., de Sousa, A. Ayres, Cibrario, G., Rozeau, O., Lacord, J., Billoint, O., Fenouillet-Beranger, C., Guissi, S., Fried, D., Morin, P., Noel, J. P., Giraud, B., Thuries, S., Arnaud, F., Vinet, M.

“…We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor,…”
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A 6-GHz Low-Power BiCMOS SiGe:C 0.25 \mu m Direct Digital Synthesizer by Thuries, S., Tournier, E., Cathelin, A., Godet, S., Graffeuil, J.

“…A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and…”
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Recent advances in 3D VLSI integration by Fenouillet-Beranger, C., Batude, P., Brunet, L., Mazzocchi, V., Lu, C.-M V., Deprat, F., Micout, J., Samson, M.-P, Previtali, B., Besombes, P., Rambal, N., Andrieu, F., Billoint, O., Brocard, M., Thuries, S., Cibrario, G., Vinet, M.

“…This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and…”
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3DVLSI with CoolCube process: An alternative path to scaling by Batude, P., Fenouillet-Beranger, C., Pasini, L., Lu, V., Deprat, F., Brunet, L., Sklenard, B., Piegas-Luce, F., Casse, M., Mathieu, B., Billoint, O., Cibrario, G., Turkyilmaz, O., Sarhan, H., Thuries, S., Hutin, L., Sollier, S., Widiez, J., Hortemel, L., Tabone, C., Samson, M.-P, Previtali, B., Rambal, N., Ponthenier, F., Mazurier, J., Beneyton, R., Bidaud, M., Josse, E., Petitprez, E., Rozeau, O., Rivoire, M., Euvard-Colnat, C., Seignard, A., Fournel, F., Benaissa, L., Coudrain, P., Leduc, P., Hartmann, J.-M, Besson, P., Kerdiles, S., Bout, C., Nemouchi, F., Royer, A., Agraffeil, C., Ghibaudo, G., Signamarcheix, T., Haond, M., Clermidy, F., Faynot, O., Vinet, M.

“…3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This…”
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Monolithic 3D integration: A powerful alternative to classical 2D scaling by Vinet, M., Batude, P., Fenouillet-Beranger, C., Clermidy, F., Brunet, L., Rozeau, O., Hartmannn, Jm, Billoint, O., Cibrario, G., Previtali, B., Tabone, C., Sklenard, B., Turkyilmaz, O., Ponthenier, F., Rambal, N., Samson, Mp, Deprat, F., Lu, V., Pasini, L., Thuries, S., Sarhan, H., Michallet, J.-E, Faynot, O.

“…Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor…”
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Impact of intermediate BEOL technology on standard cell performances of 3D VLSI by Brocard, M., Berhault, G., Thuries, S., Clermidy, F., Batude, P., Fenouillet-Beranger, C., Brunet, L., Andrieu, F., Deprat, F., Lacord, J., Rozeau, O., Cibrario, G., Billoint, O.

“…While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another…”
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A 6-GHz Low-Power BiCMOS SiGe:C 0.25 [mu] m Direct Digital Synthesizer by Thuries, S, Tournier, E, Cathelin, A, Godet, S, Graffeuil, J

“…A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and…”
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A flexible modeling environment for a NoC-based multicore architecture by Lemaire, R., Thuries, S., Heiztmann, F.

“…Following silicon technology improvements, Systems-on-Chip become more and more complex and require higher efforts for each design and validation steps. From…”
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A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit by Andrieu, F., Batude, P., Brunet, L., Fenouillet-Beranger, C., Lattard, D., Thuries, S., Billoint, O., Fournel, R., Vinet, M.

“…In this paper, we review the main opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. Simulation results show that 3D…”
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A partitioning-free methodology for optimized gate-level monolithic 3D designs by Billoint, O., Brocard, M., Thuries, S., Berhault, G., Sarhan, H.

“…This paper presents a partitioning-free algorithm that transforms a 2D design into a gate-level Monolithic 3D one, reducing design footprint by 50%, total wire…”
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3D Sequential Integration: Application-driven technological achievements and guidelines by Batude, P., Brunet, L., Fenouillet-Beranger, C., Andrieu, F., Colinge, J.-P, Lattard, D., Vianello, E., Thuries, S., Billoint, O., Vivet, P., Santos, C., Mathieu, B., Sklenard, B., Lu, C.-M V., Micout, J., Deprat, F., Mercado, E. Avelar, Ponthenier, F., Rambal, N., Samson, M.-P, Casse, M., Hentz, S., Arcamone, J., Sicard, G., Hutin, L., Pasini, L., Ayres, A., Rozeau, O., Berthelon, R., Nemouchi, F., Rodriguez, P., Pin, J.-B, Larmagnac, D., Duboust, A., Ripoche, V., Barraud, S., Allouti, N., Barnola, S., Vizioz, C., Hartmann, J.-M, Kerdiles, S., Alba, P. Acosta, Beaurepaire, S., Beugin, V., Fournel, F., Besson, P., Loup, V., Gassilloud, R., Martin, F., Garros, X., Mazen, F., Previtali, B., Euvrard-Colnat, C., Balan, V., Comboroure, C., Zussy, M., Mazzocchi, Faynot, O., Vinet, M.

“…3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<;100nm) offers new 3D partitioning options at fine granularities. This paper reviews…”
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3D sequential integration opportunities and technology optimization by Batude, P., Sklenard, B., Fenouillet-Beranger, C., Previtali, B., Tabone, C., Rozeau, O., Billoint, O., Turkyilmaz, O., Sarhan, H., Thuries, S., Cibrario, G., Brunet, L., Deprat, F., Michallet, J-E, Clermidy, F., Vinet, M.

“…Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents "true" benefits of going to the vertical dimension as the stacked layers can be…”
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Technology scaling: The CoolCubeTM paradigm by Clermidy, F., Billoint, O., Sarhan, H., Thuries, S.

“…Scaling race towards aggressive nodes is getting more and more difficult as dimensions are getting close to the atoms ones. New solutions have to be…”
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Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes by Santos, C., Vivet, P., Thuries, S., Billoint, O., Colonna, J.-P, Coudrain, P., Wang, L.

“…CoolCube™ is a monolithic 3D technology which has the potential to solve the interconnection density limitation of the existing TSV-based 3D integration…”
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