Search Results - "Teo, S.H.G."

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  1. 1

    Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET by Yang, B., Buddharaju, K.D., Teo, S.H.G., Singh, N., Lo, G.Q., Kwong, D.L.

    Published in IEEE electron device letters (01-07-2008)
    “…This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio…”
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    Journal Article
  2. 2

    Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell by Fu, J., Singh, N., Buddharaju, K.D., Teo, S.H.G., Shen, C., Jiang, Y., Zhu, C., Yu, M.B., Lo, G.Q., Balasubramanian, N., Kwong, D.L., Gnani, E., Baccarani, G.

    Published in IEEE electron device letters (01-05-2008)
    “…This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which…”
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    Journal Article
  3. 3

    CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach by Rustagi, S. C., Singh, N., Fang, W. W., Buddharaju, K. D., Omampuliyur, S. R., Teo, S. H. G., Tung, C. H., Lo, G. Q., Balasubramanian, N., Kwong, D. L.

    Published in IEEE electron device letters (01-11-2007)
    “…This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach…”
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    Journal Article
  4. 4

    Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- \kappa/Metal-Gate Device Structures by Singh, N., Fang, W.W., Rustagi, S.C., Budharaju, K.D., Teo, S.H.G., Mohanraj, S., Lo, G.Q., Balasubramanian, N., Kwong, D.-L.

    Published in IEEE electron device letters (01-07-2007)
    “…This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme…”
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    Journal Article
  5. 5
  6. 6

    Rod type photonic crystal optical line defect waveguides with optical modulations by Teo, S.H.G., Liu, A.Q., Singh, J., Yu, M.B., Lo, G.Q.

    “…This paper reports the design and principles of two dimensional rod-type photonic crystal (PhC) line defect waveguides for bandgap based optical waveguiding,…”
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    Journal Article
  7. 7

    Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- K/Metal-Gate Device Structures by Singh, N, Fang, W W, Rustagi, S C, Budharaju, K D, Teo, S.H.G., Mohanraj, S, Lo, G Q, Balasubramanian, N, Kwong, D.-L.

    Published in IEEE electron device letters (01-07-2007)
    “…This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme…”
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    Journal Article
  8. 8

    Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach by Buddharaju, K.D., Singh, N., Rustagi, S.C., Teo, S.H.G., Wong, L.Y., Tang, L.J., Tung, C.H., Lo, G.Q., Balasubramanian, N., Kwong, D.L.

    “…We present, for the first time , the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive…”
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    Conference Proceeding
  9. 9

    CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs by Yang, B., Buddharaju, K.D., Teo, S.H.G., Fu, J., Singh, N., Lo, G.Q., Kwong, D.L.

    “…We present vertical gate-all-around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up…”
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    Conference Proceeding
  10. 10

    Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory by Fu, J., Buddharaju, K.D., Teo, S.H.G., Chunxiang Zhu, Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L.

    “…Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and…”
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    Conference Proceeding
  11. 11

    Light-speed optical control with nano-opto-electronic device by Teo, S.H.G., Singh, J., Yu, M.B., Zhang, J.B., Shi, L.P., Hong, M.H., Liu, A.Q.

    “…This paper presents the design, fabrication and measurement results of a nano-photonic bandgap crystal (PhC) integrated circuit device. The PhC comprises of…”
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    Conference Proceeding
  12. 12

    Pure photonic crystal waveguiding for signal processing at optical junctions by Teo, S.H.G., Liu, A.Q., Singh, J., Yu, M.B., Wu, J.H., Zhang, X.M.

    “…This paper describes a photonic crystal (PhC) waveguide of two-dimensional (2D) photonic bandgap lattice structure. Typically, PhC waveguides demonstrated have…”
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    Conference Proceeding