Search Results - "Teo, S.H.G."
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1
Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET
Published in IEEE electron device letters (01-07-2008)“…This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio…”
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Journal Article -
2
Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell
Published in IEEE electron device letters (01-05-2008)“…This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which…”
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Journal Article -
3
CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach
Published in IEEE electron device letters (01-11-2007)“…This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach…”
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4
Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- \kappa/Metal-Gate Device Structures
Published in IEEE electron device letters (01-07-2007)“…This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme…”
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5
Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- [kappa]/Metal-Gate Device Structures
Published in IEEE electron device letters (01-07-2007)Get full text
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6
Rod type photonic crystal optical line defect waveguides with optical modulations
Published in Applied physics. A, Materials science & processing (01-11-2007)“…This paper reports the design and principles of two dimensional rod-type photonic crystal (PhC) line defect waveguides for bandgap based optical waveguiding,…”
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Journal Article -
7
Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- K/Metal-Gate Device Structures
Published in IEEE electron device letters (01-07-2007)“…This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme…”
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Journal Article -
8
Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach
Published in ESSDERC 2007 - 37th European Solid State Device Research Conference (01-09-2007)“…We present, for the first time , the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive…”
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Conference Proceeding -
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CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs
Published in ESSDERC 2008 - 38th European Solid-State Device Research Conference (01-09-2008)“…We present vertical gate-all-around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up…”
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Conference Proceeding -
10
Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory
Published in 2007 IEEE International Electron Devices Meeting (01-12-2007)“…Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and…”
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Conference Proceeding -
11
Light-speed optical control with nano-opto-electronic device
Published in 2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS) (01-01-2007)“…This paper presents the design, fabrication and measurement results of a nano-photonic bandgap crystal (PhC) integrated circuit device. The PhC comprises of…”
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Conference Proceeding -
12
Pure photonic crystal waveguiding for signal processing at optical junctions
Published in The 13th International Conference on Solid-State Sensors, Actuators and Microsystems, 2005. Digest of Technical Papers. TRANSDUCERS '05 (2005)“…This paper describes a photonic crystal (PhC) waveguide of two-dimensional (2D) photonic bandgap lattice structure. Typically, PhC waveguides demonstrated have…”
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Conference Proceeding