PCIe-Express Channel Design Optimization for Out-of-Guideline Three Connector Topology

PCI-Express (PCIe) channel design is very challenging for 32GT/s applications, and channel loss management and impedance matching are very important for system robustness, especially for the channel with multiple connection configurations. In this paper, several important design strategies were appl...

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Bibliographic Details
Published in:	2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT) pp. 1 - 4
Main Authors:	Teng, Timo, Wang, Mark, Hsu, Jimmy, Lee, Wayne, Su, Thonas, Kan, Jenny, Chen, Betty
Format:	Conference Proceeding
Language:	English
Published:	IEEE 26-10-2022
Subjects:	Connectors Impedance matching Insertion loss Micromechanical devices Packaging Robustness Topology
Online Access:	Get full text
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Summary:	PCI-Express (PCIe) channel design is very challenging for 32GT/s applications, and channel loss management and impedance matching are very important for system robustness, especially for the channel with multiple connection configurations. In this paper, several important design strategies were applied to optimize out-of-guideline three connector topology. The channel insertion loss is reduced because of lower motherboard loss meeting PCI-SIG requirements for various applications. Increased voiding in the adapter card and better cable quality were adopted to improve channel impedance matching. Intel® Automatic In-Board Characterization (AIBC) and end-to-end electrical characterization using Intel® IO Margin Tool (IOMT) were adopted to efficiently investigate the electrical design quality. Customer time-to-market was much improved because of this comprehensive analysis.
ISSN:	2150-5942
DOI:	10.1109/IMPACT56280.2022.9966687