Search Results - "Tawel, R."
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Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips
Published in IEEE transactions on very large scale integration (VLSI) systems (01-02-2001)“…Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the…”
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Evolution of analog circuits on field programmable transistor arrays
Published in Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware (2000)“…Evolvable Hardware (EHW) refers to HW design and self reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key…”
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Conference Proceeding
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Analog VLSI neural networks: implementation issues and examples in optimization and supervised learning
Published in IEEE transactions on industrial electronics (1982) (01-12-1992)“…Time-critical neural network applications that require fully parallel hardware implementations for maximal throughput are considered. The rich array of…”
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Observation of a positron mobility threshold in gaseous helium
Published in Physical review letters (26-05-1986)Get full text
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Execution of a remote sensing application on a custom neurocomputer
Published in IEEE transactions on neural networks (01-11-1995)“…A radial basis function neural network was successfully applied to an area which is relatively new for neural networks: a remote sensing application that…”
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A neural architecture for the assignment problem: simulation and VLSI implementation
Published in IJCNN-91-Seattle International Joint Conference on Neural Networks (1991)“…A competitive neural network architecture and hardware implementation is described. It is capable of solving first-order assignment problems. Each member of…”
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Conference Proceeding -
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Nonlinear functional approximation with networks using adaptive neurons
Published in [Proceedings 1992] IJCNN International Joint Conference on Neural Networks (1992)“…A novel mathematical framework for the rapid learning of nonlinear mappings and topological transformations is presented. It is based on allowing the neuron's…”
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Conference Proceeding -
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Real-time focal-plane image compression
Published in [Proceedings] DCC `93: Data Compression Conference (1993)“…A novel analog focal-plane processor, the Vector Array Processor (VAP), is designed specifically for use in real-time/video-rate on-line lossy image…”
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Conference Proceeding -
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Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits
Published in Proceedings of the First NASA/DoD Workshop on Evolvable Hardware (1999)“…The paper describes the architectural details of a fine-grained programmable transistor array (PTA) architecture and illustrates its use in evolutionary…”
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Conference Proceeding -
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Toward on-board synthesis and adaptation of electronic functions: An evolvable hardware approach
Published in 1999 IEEE Aerospace Conference. Proceedings (Cat. No.99TH8403) (1999)“…Future remote interplanetary space mission will drive the system to higher degrees of autonomy to adapt to new environments and perform new functions, beyond…”
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Conference Proceeding -
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Custom VLSI ASIC for automotive applications with recurrent networks
Published in 1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36227) (1998)“…Demands on the performance of vehicle control and diagnostic systems are steadily increasing as a consequence of stiff global competition and government…”
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Conference Proceeding -
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A CMOS UV-programmable non-volatile synaptic array
Published in IJCNN-91-Seattle International Joint Conference on Neural Networks (1991)“…A CMOS floating-gate-based nonvolatile analog circuit that implements an array of simple processing synaptic elements is described. In this implementation,…”
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Conference Proceeding -
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A radial basis function neurocomputer implemented with analog VLSI circuits
Published in [Proceedings 1992] IJCNN International Joint Conference on Neural Networks (1992)“…An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis…”
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Conference Proceeding -
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Different approaches to implementing a radial basis function neurocomputer
Published in [Proceedings] 1992 RNNS/IEEE Symposium on Neuroinformatics and Neurocomputers (1992)“…Describes and analyses three different approaches to implementing a radial basis function neural network with an electronic neurocomputer. This type of network…”
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Conference Proceeding