Search Results - "Tan Juan Boon"

3D Geometric Engineering of the Double Wedge-Like Electrodes for Filament-Type RRAM Device Performance Improvement by Sun, Jianxun, Li, Yuan Bo, Ye, Yiyang, Zhang, Jun, Chong, Gang Yih, Tan, Juan Boon, Liu, Zhen, Chen, Tupei

“…The resistive switching variability and reliability degradation are the two major challenges that hinder the high-volume production of the Resistive Random…”
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HfOx-Based RRAM Device With Sandwich-Like Electrode for Thermal Budget Requirement by Sun, Jianxun, Tan, Juan Boon, Chen, Tupei

“…The thermal budget of the standard integrated circuits (ICs) manufacturing process is one of the key considerations in the development of resistive random…”
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Underfill selection methodology for fine pitch Cu/low-k FCBGA packages by Ong, Xuefen, Ho, Soon Wee, Ong, Yue Ying, Wai, Leong Ching, Vaidyanathan, Kripesh, Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Tan, Juan Boon, Sohn, Dong Kyun, Hsia, Liang Choo, Chen, Zhong

“…A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid…”
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Investigation of Electrical Noise Signal Triggered Resistive Switching and Its Implications by Sun, Jianxun, Tan, Juan Boon, Chen, Tupei

“…In this article, the electrical noise signal triggered switching of resistive random access memory (RRAM) device is investigated. As noise is also generated…”
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HfO x -Based RRAM Device With Sandwich-Like Electrode for Thermal Budget Requirement by Sun, Jianxun, Tan, Juan Boon, Chen, Tupei

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Design, assembly and reliability of large die and fine-pitch Cu/low- k flip chip package by Ong, Yue Ying, Ho, Soon Wee, Vaidyanathan, Kripesh, Sekhar, Vasarla Nagendra, Jong, Ming Chinq, Yak Long, Samuel Lim, Wen Sheng, Vincent Lee, Wai, Leong Ching, Rao, Vempati Srinivasa, Ong, Jimmy, Ong, Xuefen, Zhang, Xiaowu, Seung, Yoon Uk, Lau, John H., Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Yanfeng, Zhang, Tan, Juan Boon, Sohn, Dong Kyun

“…This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump…”
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Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package by Yue Ying Ong, Soon Wee Ho, Sekhar, V N, Xuefen Ong, Ong, J, Xiaowu Zhang, Vaidyanathan, K, Seung Uk Yoon, Lau, J H, Lim Yeow Kheng, Yeo, D, Kai Chong Chan, Yanfeng Zhang, Juan Boon Tan, Dong Kyun Sohn

“…This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm 2 Cu/low-K flip chip packages (65 nm technology) with 150 μm…”
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Wafer level microarcing model in 90nm chemical-vapor deposition low-k via etch on 300mm silicon-on-insulator substrate by Cong, Hai, Low, Chun Hui, Pradeep, Yelehanka Ramachandramurthy, Zhang, Xin, Chandima, Perera, Liu, Wu Ping, Tan, Juan Boon, Hsia, Liang Choo

“…In SiOCH (C-doped SiO2) via etch application, high polymer deposition chemistry is needed for better selectivity to both photoresist and underlying barrier…”
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Investigation and Failure Analysis of "Flower-like" Defects on Microchip Aluminum Bondpads in Wafer Fabrication by Hua Younan, Lim Yeow Kheng, Zhao Siping, Ramesh, R., Tan Juan Boon

“…In this paper, Al fluoride defects on microchip Al bondpads were studied, which were confirmed to be due to a 12 hours delay prior to NE111 clean process…”
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Enhanced resistive switching characteristics of conductive bridging memory device by a Co–Cu alloy electrode by Lee, Calvin Xiu Xian, Dananjaya, Putu Andhita, Chee, Mun Yin, Poh, Han Yin, Tan, Funan, Thong, Jia Rui, Liu, Lingli, Lim, Gerard Joseph, Du, Yuanmin, Tan, Juan Boon, Lew, Wen Siang

“…One of the main challenges in the development of conductive bridging random access memory (CBRAM) is the large stochastic nature of ion movement that…”
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2.5D packaging solution - From concept to platform qualification by Oswald, Jens, Goetze, Christian, Shan Gao, ShunQiang Gong, Juan Boon Tan, Reed, Rick, YoungRae Kim

“…Silicon interposers offer a viable path to perpetuating the trend of increased chip performance per die area, as projected by Moore's law, which can no longer…”
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A thermo mechanical finite element modeling approach to solving stress induced passivation failures by Mirza, Fahad, Khor, E. E. Jan, Fook Hong Lee, Premachandran, C. S., Wanbing Yi, Juan Boon Tan, Graas, Carole, Justison, Patrick

“…Multi-layered systems are susceptible to cracking and or delamination upon temperature cycling. Passivation integrity test (PIT) is widely leveraged to assess…”
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Integration challenges of low temperature BEOL interconnects by Bhushan, Bharat, Yi Jiang, Wanbing Yi, Juan Boon Tan, Zhehui Wang, Chin Chuan Neo, Guoqing Lin, Kah Wee, Ju Dy, Yew Tuck Chow, Poh, Francis, Shum, Danny, Nagel, Kerry, Deshpande, Sarin, Hossain, Moazzem, Aggarwal, Sanjeev

“…We present the first exploratory low temperature, lower than standard back-end-of-line (BEOL) interconnects temperature in CMOS. The approach poses several…”
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Insights on Inter-metal Reliability Assessment of High Voltage Interconnects by Yew, Kwang Sing, Ong, Ran Xing, Yap, Hin Kiong, Yi, Wanbing, Phang, Jacquelyn, Chockalingam, R., Tan, Juan Boon

“…Reliability qualification of HV interconnects is more complicated due to the additional inter-metal impact under high voltage operation. Typically, this is…”
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Impact of pattern density on copper interconnects barrier metal liner integrity by Wanbing Yi, Daxiang Wang, Kemao Lin, Shaoqiang Zhang, Juan Boon Tan

“…The dependency of Cu interconnects barrier metal liner integrity due to neighboring pattern density is presented in this paper. It was found that TaN/Ta…”
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Foundry RF technologies by Verma, P. R., Zhang Shaoqiang, Chew Kok Wai, Tan Juan Boon, Nair, Rajesh

“…Landscape of semiconductor technologies and manufacturing has been changing in general and RF technologies in specific from IDMs to foundries and from exotic…”
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Foundry TSV integration and manufacturing challenges by Shun Qiang Gong, Wei Liu, Juan Boon Tan, Bhatkar, Mahesh, Hai Cong, Oswald, Jens, Lo, Eddy, Soh Yun Siah

“…Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect…”
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Effects of side reservoirs on the electromigration lifetime of copper interconnects by Mario, Hendro, Chee Lip Gan, Yeow Kheng Lim, Juan Boon Tan, Jun Wei, Chookajorn, Tongjai, Thompson, Carl V.

“…A new side reservoir test structure is shown to have improved electromigration reliability over conventional end-of-line reservoir structures. This is believed…”
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Fine pitch copper wire bonding on 45nm tech Cu/low-k chip with different bond pad metallurgy by Leong Ching Wai, Jaafar, N. B., Chew, M., Sivakumar, S., Gunasekaran, G., Kanchet, K., Witarsa, D., Tan Juan Boon, Srinivasa, V. R., Chai, T. C., Alastair, A., Woo, J.

“…Wire bonding technology has been widely used in the semiconductor industry for interconnection between device and substrate. Gold wire has been used in…”
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EELS chemical bond characterization of process induced damages in low-k dielectric films by YongKai Zhou, Jie Zhu, AnYan Du, YouNan Hua, SiPing Zhao, Wei Liu, Fan Zhang, Juan Boon Tan

“…EELS chemical bond analysis has been used to characterize etching process induced plasma damages in low-k SiCOH materials. EELS can provide not only the…”
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