Search Results - "TSUKUDE, M"

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs by Yamagata, T., Tomishima, S., Tsukude, M., Tsuruda, T., Hashizume, Y., Arimoto, K.

“…This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL)…”
Get full text

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme by Tsukude, M., Kuge, S., Fujino, T., Arimoto, K.

“…A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V/sub cc/ bit-line precharge achieves a five times larger readout voltage and…”
Get full text

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's by Tsuruda, T., Kobayashi, M., Tsukude, M., Yamagata, T., Arimoto, K., Yamada, M.

“…Recently, as multimedia large scale integrated devices (LSIs) have developed, there has been strongly increased demand for high-speed/high-bandwidth LSIs which…”
Get full text

400-MHz random column operating SDRAM techniques with self-skew compensation by Hamamoto, T., Tsukude, M., Arimoto, K., Konishi, Y., Miyamoto, T., Ozaki, H., Yamada, M.

“…High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed…”
Get full text

An experimental 256-Mb DRAM with boosted sense-ground scheme by Asakura, M., Ooishi, T., Tsukude, M., Tomishima, S., Eimori, T., Hidaka, H., Ohno, Y., Arimoto, K., Fujishima, K., Nishimura, T., Yoshihara, T.

“…In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the…”
Get full text

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture by Sakashita, N., Nitta, Y., Shimomura, K., Okuda, F., Shimano, H., Yamakawa, S., Tsukude, M., Arimoto, K., Baba, S., Komori, S., Kyuma, K., Yasuoka, A., Abe, H.

“…This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are…”
Get full text

SOI-DRAM circuit technologies for low power high speed multigiga scale memories by Kuge, S., Morishita, F., Tsuruda, T., Tomishima, S., Tsukude, M., Yamagata, T., Arimoto, K.

“…This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of…”
Get full text

A 34-ns 16-Mb DRAM with controllable voltage down-converter by Hidaka, H., Arimoto, K., Hirayama, K., Hayashikoshi, M., Asakura, M., Tsukude, M., Oishi, T., Kawai, S., Suma, K., Konishi, Y., Tanaka, K., Wakamiya, W., Ohno, Y., Fujishima, K.

“…A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme…”
Get full text

Circuit design techniques for low-voltage operating and/or giga-scale DRAMs by Yamagata, T., Tomishima, S., Tsukude, M., Hashizume, Y., Arimoto, K.

“…As use of battery-operated machines, such as hand-held computers and PDAs, becomes wider, low-voltage/low-power DRAMs are required. Low-voltage technologies…”
Get full text

Low-temperature SiO2 growth using fluorine-enhanced thermal oxidation by MORITA, M, ARITOME, S, TSUKUDE, M, MURAKAWA, T, HIROSE, M

“…A new low-temperature oxidation technique of silicon to obtain high quality Si-SiO2 interface and bulk SiO2 layer is presented. A few tens-nanometer-thick…”
Get full text

A speed-enhanced DRAM array architecture with embedded ECC by Arimoto, K., Matsuda, Y., Furutani, K., Tsukude, M., Ooishi, T., Mashiko, K., Fujishima, K.

“…An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a…”
Get full text

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register by Arimoto, K., Fujishima, K., Matsuda, Y., Tsukude, M., Oishi, T., Wakamiya, W., Satoh, S., Yamada, M., Nakano, T.

“…A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array…”
Get full text

Dynamic floating body control SOI CMOS circuits for power managed multimedia ULSIs by Morishita, F., Tsukude, M., Arimoto, K.

“…A novel body potential controlling technique for floating SOI CMOS circuits is proposed and verified. High speed operation is realized with a small chip size…”
Get full text

High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs by Tsuruda, T., Kobayashi, I., Tsukude, M., Yamagata, T., Arimoto, K.

“…Recently, as multimedia LSIs have developed, the demand for high-speed/high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have…”
Get full text

A long data retention SOI-DRAM with the body refresh function by Tomishima, S., Morishita, F., Tsukude, M., Yamagata, T., Arimoto, K.

“…We have proposed a body refresh function and circuits for SOI DRAMs. The body refresh utilizes a swinging of the bit line and gives stable body potential, long…”
Get full text

Highly reliable testing of ULSI memories with on-chip voltage-down converters by Tsukude, M., Arimoto, K., Hidaka, H., Konishi, Y., Hayashikoshi, M., Suma, K., Fujishima, K.

“…Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip…”
Get full text

A 1.2-to 3.3-V wide voltage-range/low-power DRAM with acharge-transfer presensing scheme by Tsukude, M, Kuge, S, Fujino, T, Arimoto, K

“…A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V(cc) bit-line precharge achieves a five times larger readout voltage and 40%…”
Get full text

A 1.2 V to 3.3 V wide-voltage-range DRAM with 0.8 V array operation by Tsukude, M., Kuge, S., Fujino, T., Arimoto, K.

“…DRAM arrays operating with power supply below 1 V, with stable sensing and high speed are required for multi-media systems. Reduction of data-retention current…”
Get full text

A Testing Technique for ULSI Memory with On-chip Voltage Down Converter by Tsukude, M., Arimoto, K., Hidaka, H., Konishi, Y., Hayashikoshi, M.

Get full text

A smart design methodology for advanced memories by Arimoto, K., Asakura, M., Tsukude, M., Hidaka, H., Fujishima, K.

“…The authors propose a smart design methodology for advanced memories to reduce the turn around time for circuit revisions with no area penalty. This method was…”
Get full text