Search Results - "TRAVALY, Youssef"

Bottom-Up Engineering of Subnanometer Copper Diffusion Barriers Using NH2-Derived Self-Assembled Monolayers by Caro, Arantxa Maestre, Armini, Silvia, Richard, Olivier, Maes, Guido, Borghs, Gustaaf, Whelan, Caroline M., Travaly, Youssef

“…A 3‐aminopropyltrimethoxysilane‐derived self‐assembled monolayer (NH2SAM) is investigated as a barrier against copper diffusion for application in…”
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Characterization and optimization of porogen-based PECVD deposited extreme low- k materials as a function of UV-cure time by Verdonck, Patrick, De Roest, David, Kaneko, Shinya, Caluwaerts, Rudy, Tsuji, Naoto, Matsushita, Kiyohiro, Kemeling, Nathan, Travaly, Youssef, Sprey, Hessel, Schaekers, Marc, Beyer, Gerald

“…A promising method to produce low- k films with a dielectric constant, k, less than 2.3, consists in using a porogen-based PECVD process in combination with UV…”
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On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing by Civale, Yann, Croes, Kristof, Miyamori, Yuichi, Velenis, Dimitrios, Redolfi, Augusto, Thangaraju, Sarasvathi, Ammel, Annemie Van, Cherman, Vladimir, Plas, Geert Van der, Cockburn, Andrew, Gravey, Virginie, Kumar, Nirajan, Cao, Zhitao, Travaly, Youssef, Tőkei, Zsolt, Beyne, Eric, Swinnen, Bart

“…Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and…”
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On a More Accurate Assessment of Scaled Copper/Low-k Interconnects Performance by Travaly, Y., Mandeep, B., Carbonell, L., Tokei, Z., Van Olmen, J., Iacopi, F., Van Hove, M., Stucchi, M., Maex, K.

“…Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity (rho Cu ), is an important…”
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Preface by Travaly, Youssef, Detavernier, Christophe

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Design Issues and Considerations for Low-Cost 3-D TSV IC Technology by Van der Plas, G, Limaye, P, Loi, I, Mercha, A, Oprins, H, Torregiani, C, Thijs, S, Linten, D, Stucchi, M, Katti, G, Velenis, D, Cherman, V, Vandevelde, B, Simons, V, De Wolf, I, Labie, R, Perry, D, Bronckers, S, Minas, N, Cupac, M, Ruythooren, W, Van Olmen, J, Phommahaxay, A, de Potter de ten Broeck, M, Opdebeeck, A, Rakowski, M, De Wachter, B, Dehan, M, Nelis, M, Agarwal, R, Pullini, A, Angiolini, F, Benini, L, Dehaene, W, Travaly, Y, Beyne, E, Marchal, P

“…In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is…”
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Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications by Jourdain, A., Buisson, T., Phommahaxay, A., Redolfi, A., Thangaraju, S., Travaly, Y., Beyne, E., Swinnen, B.

“…Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and…”
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Conference organization by Travaly, Youssef H.

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The 2010 International workshop on Materials for Advanced Metallization - MAM 2010 by TRAVALY, Youssef, DETAVERNIER, Christophe

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Bottom‐Up Engineering of Subnanometer Copper Diffusion Barriers Using NH 2 ‐Derived Self‐Assembled Monolayers by Caro, Arantxa Maestre, Armini, Silvia, Richard, Olivier, Maes, Guido, Borghs, Gustaaf, Whelan, Caroline M., Travaly, Youssef

“…A 3‐aminopropyltrimethoxysilane‐derived self‐assembled monolayer (NH 2 SAM) is investigated as a barrier against copper diffusion for application in…”
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3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias by Civale, Y, Tezcan, D S, Philipsen, H G G, Duval, F F C, Jaenen, P, Travaly, Y, Soussan, P, Swinnen, B, Beyne, E

“…In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a…”
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Design issues and considerations for low-cost 3D TSV IC technology by Van der Plas, G., Limaye, P., Mercha, A., Oprins, H., Torregiani, C., Thijs, S., Linten, D., Stucchi, M., Guruprasad, K., Velenis, D., Shinichi, D., Cherman, V., Vandevelde, B., Simons, V., De Wolf, I., Labie, R., Perry, D., Bronckers, S., Minas, N., Cupac, M., Ruythooren, W., Van Olmen, J., Phommahaxay, A., de Potter de ten Broeck, M., Opdebeeck, A., Rakowski, M., De Wachter, B., Dehan, M., Nelis, M., Agarwal, R., Dehaene, W., Travaly, Y., Marchal, P., Beyne, E.

“…We investigate key design issues of a low-cost 3D Cu-TSV technology: impact of TSV on MOS devices and interconnect, reliability, thermal hot spots, ESD, signal…”
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Lateral solvent diffusion characterization of low k dielectric plasma damage and ALD barrier film closure by Abell, Thomas, Schuhmacher, Jorg, Tokei, Zsolt, Travaly, Youssef, Maex, Karen

“…The lateral diffusion of toluene solvent molecules was employed to probe the porous structures of plasma damaged low k dielectrics and ultra-thin ALD copper…”
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Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions by Van der Plas, G, Thijs, S, Linten, D, Katti, G, Limaye, P, Mercha, A, Stucchi, M, Oprins, H, Vandevelde, B, Minas, N, Cupac, M, Dehan, M, Nelis, M, Agarwal, R, Dehaene, W, Travaly, Y, Beyne, E, Marchal, P

“…We describe the design challenges for a low-cost 130nm 3D CMOS technology with 5μm diameter at 10μm pitch Cu-TSV. We investigate electrical, thermal and…”
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Microlithographically patterned glass surfaces for directing neuronal cell outgrowth: characterization by X-ray photoelectron spectroscopy by Schmalenberg, Kristine, Dukovic, Gordana, Travaly, Youssef, Thompson, Deanna, Buettner, Helen, Uhrich, Kathryn

“…Microlithographically patterned glass surfaces were evaluated by XPS. By analyzing the peaks of carbon, oxygen, and nitrogen, it was possible to determine how…”
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Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure by Yu Yang, Katti, Guruprasad, Labie, Riet, Travaly, Youssef, Verlinden, Bert, De Wolf, Ingrid

“…Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking…”
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300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications by Jourdain, A, Buisson, T, Phommahaxay, A, Privett, M, Wallace, D, Sood, S, Bisson, P, Beyne, E, Travaly, Y, Swinnen, B

“…Thin wafer handling has become a very challenging topic of emerging 3D technologies, and temporary wafer bonding to a carrier support wafer is one way to…”
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Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's by Halder, S., Jourdain, A., Claes, M., de Wolf, I., Travaly, Y., Beyne, E., Swinnen, B., Pepper, V., Guittet, P-Y, Savage, G., Markwort, L.

“…New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically…”
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Link between silica-metal agglomeration and high porosity ultra-low k scratch formation during Chemical Mechanical Polishing by Heylen, Nancy, Camerotto, Elisabeth, Volders, Henny, Travaly, Youssef, Vereecke, Guy, Beyer, Gerald P, Tokei, Zsolt

“…Sub-surface hydrophilisation and an increase in effective k is known as damage to a highly porous ultra-low k (ULK) film when removing a metal layer from this…”
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Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions by Marchal, Paul, Van der Plas, Geert, Limaye, Paresh, Mercha, Abdelkarim, Cherman, Vladimir, O'Prins, Herman, Labie, Riet, Vandevelde, Bart, Travaly, Youssef, Beyne, Eric

“…The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we'll indicate the importance of thermal…”
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