Search Results - "TOKEI, Z"

Damage free integration of ultralow-k dielectrics by template replacement approach by Zhang, L., de Marneffe, J.-F., Heylen, N., Murdoch, G., Tokei, Z., Boemmels, J., De Gendt, S., Baklanov, M. R.

“…Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme…”
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Integration of a Stacked Contact MOL for Monolithic CFET by Vega-Gonzalez, Victor, Radisic, D., Chan, Bt, Choudhury, S., Wang, S., Mingardi, A., Le, Q. Toan, Decoster, H., Oniki, Y., Puttarame, P., Vandersmissen, K., Soulie, J.-P., Peter, A., Batuk, A. Sepulveda. D., Martinez, G. T., Richard, O., Boemmels, J., Biesemans, S., Dentoni, E., Horiguchi, N., Park, S., Tokei, Z.

“…Complementary FET (CFET) is a device architecture where n-and p-MOS transistors are stacked. As a result, the source and drain contact metals also need to be…”
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Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling by Vandevelde, Bart, Ivankovic, A., Debecker, B., Lofrano, M., Vanstreels, K., Guo, W., Cherman, V., Gonzalez, M., Van der Plas, G., De Wolf, I., Beyne, E., Tokei, Z.

“…•Analytical modelling, FEM simulations and 4 point bending for BEOL strength analysis.•Reduced low-k stiffness results in exponential growth of stress in Cu…”
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Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips by Samavedam, S. B., Ryckaert, J., Beyne, E., Ronse, K., Horiguchi, N., Tokei, Z., Radu, I., Bardon, M. G., Na, M. H., Spessot, A., Biesemans, S.

“…With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance…”
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Selective self-assembled monolayer coating to enable Cu-to-Cu connection in dual damascene vias by Maestre Caro, A., Travaly, Y., Beyer, G., Tokei, Z., Maes, G., Borghs, G., Armini, S.

“…In order to enable an oxide-free Cu-to-Cu bonding in a (dual) damascene process, 3-aminopropyltrimethoxysilane- and decanethiol-derived self-assembled…”
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Holisitic device exploration for 7nm node by Raghavan, P., Bardon, M. Garcia, Jang, D., Schuddinck, P., Yakimets, D., Ryckaert, J., Mercha, A., Horiguchi, N., Collaert, N., Mocuta, A., Mocuta, D., Tokei, Z., Verkest, D., Thean, A., Steegen, A.

“…In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power…”
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Vertical device architecture for 5nm and beyond: Device & circuit implications by Thean, A. V.-Y, Yakimets, D., Huynh Bao, T., Schuddinck, P., Sakhare, S., Bardon, M. Garcia, Sibaja-Hernandez, A., Ciofi, I., Eneman, G., Veloso, A., Ryckaert, J., Raghavan, P., Mercha, A., Mocuta, A., Tokei, Z., Verkest, D., Wambacq, P., De Meyer, K., Collaert, N.

“…Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we…”
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Directional Etching of Barrierless NiAl Lines on 300-mm Wafers for Interconnects Applications by Kundu, Souvik, Soulie, J.-P., Marti, G., Okudur, F. U., Kundu, Shreya, Souriau, L., Lazzarino, F., Murdoch, G., Park, S., Tokei, Z.

“…This letter demonstrates the functionality of barrier-less 20nm NiAl for 100nm metal pitch interconnects fabricated on 300mm full wafers. We have developed an…”
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Materials characterization of WNxCy, WNx and WCx films for advanced barriers by Volders, H, Tokei, Z, Bender, H, Brijs, B, Caluwaerts, R, Carbonell, L, Conard, T, Drijbooms, C, Franquet, A, Garaud, S, Hoflijk, I, Moussa, A, Sinapi, F, Travaly, Y, Vanhaeren, D, Vereecke, G, Zhao, C, Li, W-M, Sprey, H

“…A ternary WNxCy system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 deg C in a process sequence using tungsten hexafluoride…”
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Electrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill by Leaming-Sphabmixay, K., Van Olmen, J., Moon, K.J., Vanstreels, Kris, D’Haen, J., Tokei, Z., List, S., Beyer, G.

“…The fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 30–40 nm were achieved. With an…”
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3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling by Horiguchi, N., Mertens, H., Chiarella, T., Demuynck, S., Vega-Gonzalez, V., Vandooren, A., Veloso, A., Bardon, M. Garcia, Sisto, G., Gupta, A., Tokei, Z., Biesemans, S., Ryckaert, J.

“…3D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL…”
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Electrical performance, reliability and microstructure of sub-45nm copper damascene lines fabricated with TEOS backfill by Leaming-Sphabmixay, K, Van Olmen, J, Moon, K J, Vanstreels, Kris, D'Haen, J, Tokei, Z, List, S, Beyer, G

“…The fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 30-40nm were achieved. With an…”
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Selective ALD Mo Deposition in 10nm Contacts by van der Veen, Marleen H., Maes, J. W., Pedreira, O. Varela, Zhu, C., Tierno, D., Datta, S., Jourdan, N., Decoster, S., Wu, C., Mousa, M., Byun, Y., Struyf, H., Park, S., Tokei, Z.

“…Selective atomic layer deposition (ALD) of Mo is explored to fill 10nm contacts in a 2 nm node test vehicle. The ALD Mo deposition is highly selective towards…”
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Improving uniformity of 3-level High Aspect Ratio Supervias by Montero, D., Marien, P., Hermans, Y., Vega-Gonzalez, V., Feurprier, Y., Oikawa, N., Buccheri, N., Wu, C., Martinez, G.T., Batuk, D., Puliyalil, H., Decoster, S., Kumar, K., Lazzarino, F., Murdoch, G., Park, S., Tokei, Z.

“…High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 12.1 nm, AR = 9.4 and with > 93 % electrically active SV are successfully integrated…”
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Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster by Marien, P., Gonzalez, V. V., Choudhury, S., Radisic, D., Decoster, S., Kundu, S., Hermans, Y., Kenens, B., De Coster, H., Sanchez, E. A., Peter, A., Marquez, A. S., Jourdan, N., Batuk, D., Ryckaert, J., Murdoch, G., Park, S., Tokei, Z.

“…As further scaling of standard cells (SC) continues, new innovative techniques are required to the keep pursuing Moore's law. Middle-of-line (MOL) scaling…”
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On a More Accurate Assessment of Scaled Copper/Low-k Interconnects Performance by Travaly, Y., Mandeep, B., Carbonell, L., Tokei, Z., Van Olmen, J., Iacopi, F., Van Hove, M., Stucchi, M., Maex, K.

“…Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity (rho Cu ), is an important…”
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Electromigration and stress-induced-voiding in dual damascene Cu/low-k interconnects: a complex balance between vacancy and stress gradients by Croes, K, Wilson, C J, Lofrano, M, Vereecke, B, Beyer, G P, Tökei, Z

“…The influence of residual vacancy concentrations and stress gradients on electromigration both in the metal layer below and above copper via's with a diameter…”
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Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below by Montero, D., Vega-Gonzalez, V., Feurprier, Y., Pedreira, O. Varela, Oikawa, N., Martinez, G.T., Batuk, D., Puliyalil, H., Versluijs, J., Decoster, H., Bazzazian, N., Jourdan, N., Kumar, K., Lazzarino, F., Murdoch, G., Park, S., Tokei, Z.

“…High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 15.5 nm and AR = 7.7 are successfully integrated in a 3nm node chip. 3-level SV…”
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Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond by Gupta, A., Pedreira, O. Varela, Tao, Z., Mertens, H., Radisic, D., Jourdan, N., Devriendt, K., Heylen, N., Wang, S., Chehab, B., Jang, D., Hellings, G., Sebaai, F., Lorant, C., Teugels, L., Peter, A., Chan, BT, Schleicher, F., Demonie, I., Marien, P., Sepulveda, A., Richard, O., Nagesh, N., Lesniewska, A., Lazzarino, F., Ryckaert, J., Morin, P., Altamirano-Sanchez, E., Murdoch, G., Bommels, J., Demuynck, S., Na, M. H, Tokei, Z., Biesemans, S., Litta, E. Dentoni, Horiguchi, N.

“…This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru-…”
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Volume diffusion of iron in Fe3Al: Influence of ordering by Toˆkei, Zs, Bernardini, J., Gas, P., Beke, D.L.

“…The lattice self diffusion coefficient of 59Fe in Fe3Al has been determined in the temperature range 847–1503 K using the classical radio-tracer method. Below…”
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