A wide-range and harmonic-free SAR all-digital delay locked loop

A delay locked loop (DLL) using the shift-counting type successive approximation register to control the digital delay line is proposed. It mainly can solve the problem of harmonic lock. The delay line is implemented by the complementary way to improve the range of lockable. In addition, the coarse...

Full description

Saved in:

Bibliographic Details
Published in:	2015 15th International Symposium on Communications and Information Technologies (ISCIT) pp. 197 - 200
Main Authors:	Ko-Chi Kuo, Sz-Hsien Li
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-10-2015
Subjects:	Clocks complementary Computer architecture Delay lines delay locked loop (DLL) Delays harmonic locking Logic gates Radiation detectors Registers resolution successive approximation register (SAR)
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Description
Summary:	A delay locked loop (DLL) using the shift-counting type successive approximation register to control the digital delay line is proposed. It mainly can solve the problem of harmonic lock. The delay line is implemented by the complementary way to improve the range of lockable. In addition, the coarse and fine delay cell are also utilized to improve the resolution of delay. This delay locked loop uses a 10-bit successive approximation register to achieve the fast locking. In addition, the locking range is from 100 MHz to 1 GHz. The supply voltage is 1.2V with the TSMC 90nm process. The delay resolution is about 4 ps. The power is 0.38 mW at 100 MHz and 0.9 mW at 1 GHz. The jitter is 8.8 ps at 100 MHz and 2.6 ps at 1 GHz. The lock time is 40 clock cycles at 100MHz and 24 clock cycles at 1 GHz.
DOI:	10.1109/ISCIT.2015.7458341