Search Results - "Sulaiman, Mohd. S."
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1
A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique
Published in Analog integrated circuits and signal processing (01-06-2006)“…In this paper, the design of a high-speed low-voltage CMOS interpolation with flash analog-to-digital converter (ADC) in CMOS 0.18-mum process is presented…”
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Journal Article -
2
Honey--a novel antidiabetic agent
Published in International journal of biological sciences (01-01-2012)“…Diabetes mellitus remains a burden worldwide in spite of the availability of numerous antidiabetic drugs. Honey is a natural substance produced by bees from…”
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Journal Article -
3
A 2.4-GHz, 3.74-mW CMOS PLL-based frequency synthesizer
Published in ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) (2002)“…A low-power high-performance PLL-based frequency synthesizer architecture is presented. The PLL was designed based on advanced low-power approaches such as…”
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Conference Proceeding
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4
A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint
Published in ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) (2002)“…A heuristic algorithm for optimized clock network design is presented. The algorithms for optimization of clock skew, delay, and power considering slew rate…”
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Conference Proceeding -
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A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer
Published in ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) (2002)“…A low-power high-speed programmable dual modulus divider architecture is presented. The circuit's three building blocks: prescaler, 2- and 5-bit programmable…”
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Conference Proceeding -
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A 160-Mhz 45-mW Asynchronous Dual-Port 1-Mb CMOS SRAM
Published in 2005 IEEE Conference on Electron Devices and Solid-State Circuits (2005)“…A 160-Mhz 45-mW asynchronous dualport 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data…”
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Conference Proceeding -
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A single clock cycle MIPS RISC processor design using VHDL
Published in ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) (2002)“…This paper describes a design methodology of a single clock cycle MIPS RISC Processor using VHDL to ease the description, verification, simulation and hardware…”
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Conference Proceeding -
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Pipeline floating point ALU design using VHDL
Published in ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) (2002)“…A pipeline floating point arithmetic logic unit (ALU) design using VHDL is introduced. The novelty of the ALU is it gives high performance through the…”
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Conference Proceeding