Implementation of An Energy-Efficient Binary Square Rooter Using Reversible Logic By Applying The Non-Restoring Algorithm

Calculation of square root will be an essential mathematical operation that will have broad applications. In Hardware, the square root will be designed in order to gain power which will be quite low. Similarly, there are also other advantages that comes with gaining of low power that is high speed a...

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Bibliographic Details
Published in:	2021 2nd International Conference on Communication, Computing and Industry 4.0 (C2I4) pp. 1 - 6
Main Authors:	Swathi, S., Sushma, S., Bindusree, V., Babitha, L, Sukesh, Goud K., Venkateswarlu, S. China, Vijay, V., Vallabhuni, Rajeev Ratna
Format:	Conference Proceeding
Language:	English
Published:	IEEE 16-12-2021
Subjects:	Adaptation models Binary Square rooter Conventional logic Energy efficiency Energy Efficient Logic gates Low power Multiplexing Non-restoring algorithm Reversible Reversible computing Software algorithms VHDL
Online Access:	Get full text
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Summary:	Calculation of square root will be an essential mathematical operation that will have broad applications. In Hardware, the square root will be designed in order to gain power which will be quite low. Similarly, there are also other advantages that comes with gaining of low power that is high speed and also low area. A trade-off will also occur with the three metrics which is quite natural. As we know that the present technology is very advanced so it will aim for low power and architectural modification will be required by the relative designs. This sheet represents an energy efficient square rooter by using reversible logic. (RCSM) Reversible Controlled Subtract Multiplexer will be designing and it also plays an important part in implementing the binary square rooter. Saimur Rahman Gate will also be implementing the binary square rooter in order to improve and develop it. The Improvements such as cost of the quanta, inputs given by constants and also garbage outputs. The approaches such as conventional approach and SRG are used for designing the binary square rooter and it will be completed using non-restoring algorithm. Xilinx Software will be responsible for carrying out simulations and Synopsys Design Compiler will be the factor for obtaining power. The gate count which has been 75 will be decreased to 35. There will be an improvement of 20% in terms of power which will be obtained in this paper.
DOI:	10.1109/C2I454156.2021.9689438