Search Results - "Suh, G. E."

Extracting secret keys from integrated circuits by Daihyun Lim, Lee, J.W., Gassend, B., Suh, G.E., van Dijk, M., Devadas, S.

“…Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However,…”
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Dynamic Partitioning of Shared Cache Memory by Suh, G. E., Rudolph, L., Devadas, S.

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Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions by Suh, G Edward, O'Donnell, Charles W, Sachdev, Ishan, Devadas, Srinivas

“…Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the…”
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Caches and hash trees for efficient memory integrity verification by Gassend, B., Suh, G.E., Clarke, D., van Dijk, M., Devadas, S.

“…We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could…”
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A new memory monitoring scheme for memory-aware scheduling and partitioning by Suh, G.E., Devadas, S., Rudolph, L.

“…We propose a low overhead, online memory monitoring scheme utilizing a set of novel hardware counters. The counters indicate the marginal gain in cache hits as…”
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High-performance parallel accelerator for flexible and efficient run-time monitoring by Deng, Daniel Y., Suh, G. E.

“…This paper proposes Harmoni, a high performance hardware accelerator architecture that can support a broad range of run-time monitoring and bookkeeping…”
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Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints by Yinglei Wang, Wing-kei Yu, Shuo Wu, Malysa, G., Suh, G. E., Kan, E. C.

“…We demonstrate that unmodified commercial Flash memory can provide two important security functions: true random number generation and digital fingerprinting…”
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Optimal and Heuristic Application-Aware Oblivious Routing by Kinsy, M. A., Myong Hyon Cho, Keun Sup Shim, Lis, M., Suh, G. E., Devadas, S.

“…Conventional oblivious routing algorithms do not take into account resource requirements (e.g., bandwidth, latency) of various flows in a given application. As…”
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Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric by Deng, D Y, Lo, D, Malysa, G, Schneider, S, Suh, G E

“…This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core…”
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Efficient memory integrity verification and encryption for secure processors by Suh, G.E., Clarke, D., Gasend, B., van Dijk, M., Devadas, S.

“…Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security…”
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Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis by Ismail, M., Suh, G. E.

“…Recent work has shown that hardware-based runtime monitoring techniques can significantly enhance security and reliability of computing systems with minimal…”
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Efficient Timing Channel Protection for On-Chip Networks by Yao Wang, Suh, G. E.

“…On-chip network is often dynamically shared among applications that are concurrently running on a chip-multiprocessor (CMP). In general, such shared resources…”
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Hiding Information in Flash Memory by Yinglei Wang, Wing-kei Yu, Xu, S. Q., Kan, E., Suh, G. E.

“…This paper introduces a novel information hiding technique for Flash memory. The method hides data within an analog characteristic of Flash, the program time…”
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Precise exception support for decoupled run-time monitoring architectures by Deng, D. Y., Suh, G. E.

“…Recently, researchers have proposed decoupled monitoring architectures that utilize parallel hardware such as multi-cores or accelerators to enable…”
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Speeding up Exponentiation using an Untrusted Computational Resource by Van Dijk, Marten, Clarke, Dwaine, Gassend, Blaise, Suh, G. Edward, Devadas, Srinivas

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Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions by Suh, G. Edward, O'Donnell, Charles W., Sachdev, Ishan, Devadas, Srinivas

“…Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the…”
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A non-volatile microcontroller with integrated floating-gate transistors by Wing-kei Yu, Rajwade, S., Sung-En Wang, Lian, B., Suh, G. E., Kan, E.

“…We present a non-volatile processor architecture where its entire state can be almost instantly stored and restored in a non-volatile fashion. This capability…”
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On the performance of averaged optimal routing by Michael, N., Ao Tang, Suh, G. E.

“…Traffic uncertainty makes designing optimal routing protocols for many networks a difficult problem. A good way to capture uncertainty is via an uncertainty…”
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FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric by Lo, D., Malysa, G., Suh, G. E.

“…In today's microprocessors, the cache architecture is highly optimized for one particular design and cannot be changed after fabrication. While allowing…”
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Analysis of application-aware on-chip routing under traffic uncertainty by Michael, Nithin, Nikolov, Milen, Tang, Ao, Suh, G. Edward, Batten, Christopher

“…Application-aware routing exploits static knowledge of an application's traffic pattern to improve performance compared to generalpurpose routing algorithms…”
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