Search Results - "Strollo, Antonio G. M."

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error by Petra, Nicola, De Caro, Davide, Garofalo, Valeria, Napoli, Ettore, Strollo, Antonio G M

“…Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where…”
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Efficient Logarithmic Converters for Digital Signal Processing Applications by De Caro, Davide, Petra, N., Strollo, A. G. M.

“…The hardware computation of the logarithm function is required in a multitude of applications. This brief investigates logarithmic converters based on…”
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Approximate Full-Adders: A Comprehensive Analysis by Napoli, Ettore, Zacharelos, Efstratios, Strollo, Antonio G. M., Di Meo, Gennaro

“…Approximate computing is a technique that sacrifices the accuracy of the result for an advantage in terms of power, area, and speed. It is useful for…”
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Accurate Fixed-Point Logarithmic Converter by De Caro, Davide, Genovese, Mariangela, Napoli, Ettore, Petra, Nicola, Strollo, Antonio G. M.

“…The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems…”
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Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines by De Caro, Davide, Tessitore, Fabio, Vai, Gianfranco, Castellano, Gerardo, Napoli, Ettore, Petra, Nicola, Parrella, Claudio, Strollo, Antonio G. M.

“…NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy standard…”
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Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding by De Caro, Davide, Napoli, Ettore, Esposito, Darjn, Castellano, Gerardo, Petra, Nicola, Strollo, Antonio G. M.

“…Piecewise polynomial interpolation is a well-established technique for hardware function evaluation. The paper describes a novel technique to minimize…”
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Approximate Recursive Multipliers Using Low Power Building Blocks by Zacharelos, Efstratios, Nunziata, Italo, Saggese, Gerardo, Strollo, Antonio G.M., Napoli, Ettore

“…Approximate computing, frequently used in error tolerant applications, aims to achieve higher circuit performances by allowing the possibility of inaccurate…”
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Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor by Strollo, Antonio G. M., De Caro, Davide, Napoli, Ettore, Petra, Nicola, Di Meo, Gennaro

“…In this paper we propose an energy-efficient approximate multiplier which uses a new approximate 4-2 compressor. The proposed compressor has a low error…”
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Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic by Esposito, Darjn, De Caro, Davide, Di Meo, Gennaro, Napoli, Ettore, Strollo, Antonio G. M.

“…Adaptive filters based on least-mean-square (LMS) algorithm are used in several applications in virtue of their good steady-state performance, numerical…”
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A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS by De Caro, Davide, Tessitore, Fabio, Vai, Gianfranco, Imperato, Nicola, Petra, Nicola, Napoli, Ettore, Parrella, Claudio, Strollo, Antonio G. M.

“…Spread-spectrum clocking is an established approach to mitigate electromagnetic interference (EMI) of digital circuits, by intentionally sweeping the clock…”
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FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video by Petra, Nicola, Napoli, Ettore, De Caro, Davide, Strollo, Antonio G. M., Genovese, Mariangela

“…Circuits and systems able to process high quality video in real time are fundamental in nowadays imaging systems. The circuit proposed in the paper, aimed at…”
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A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate by Napoli, Ettore, De Caro, Davide, Petra, Nicola, Strollo, Antonio G. M.

“…Video processing requires an increasing amount of buffered data. The paper proposes a multi-line buffer circuit that stores compressed data thus saving logic…”
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A SISO Register Circuit Tailored for Input Data with Low Transition Probability by Napoli, Ettore, Castellano, Gerardo, De Caro, Davide, Esposito, Darjn, Petra, Nicola, Strollo, Antonio G. M.

“…The paper proposes a SISO register circuit, functionally equivalent to a Shift Register, that is the optimal design choice when the input data have a reduced…”
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Comprehensive Analysis of Input Order Invariant Approximate 4-2 Compressors for Binary Multipliers by Napoli, Ettore, Strollo, Antonio G.M., Zacharelos, Efstratios, Di Meo, Gennaro

“…Approximate arithmetic circuits sacrifice computing accuracy in exchange for improvements in power, area, and speed. Many approximate binary multipliers that…”
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High-Performance Special Function Unit for Programmable 3-D Graphics Processors by De Caro, Davide, Petra, Nicola, Strollo, Antonio G. M.

“…An high-speed special function unit (SFU) is presented in this paper. The system supports the single-precision IEEE-754 floating-point standard and implements…”
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Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA by Genovese, Mariangela, Napoli, Ettore, De Caro, Davide, Petra, Nicola, Strollo, Antonio G.M.

“…The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems. The recent…”
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Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations by Strollo, Antonio G M, De Caro, Davide, Petra, Nicola

“…A novel technique for designing piecewise-polynomial interpolators for hardware implementation of elementary functions is investigated in this paper. In the…”
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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-μm CMOS by BONFANTI, Andrea, DE CARO, Davide, GRASSO, Alfio Dario, PENNISI, Salvatore, SAMORI, Carlo, STROLLO, Antonio G. M

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A 41 ps ASIC time-to-digital converter for physics experiments by Russo, Stefano, Petra, Nicola, De Caro, Davide, Barbarino, Giancarlo, Strollo, Antonio GM

“…We present a novel Time-to-Digital (TDC) converter for physics experiments. Proposed TDC is based on a synchronous counter and an asynchronous fine…”
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Design of a Hardware-Efficient Floating-Point Multiplier with Dynamic Segmentation by Tegazzini, Luca, Di Meo, Gennaro, De Caro, Davide, Strollo, Antonio G. M.

“…In this paper, we present a novel low-power floating-point multiplier design that leverages dynamic segmentation to enhance efficiency. Our approach…”
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