Search Results - "Storino, S.N."

A 440-ps 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology by Stasiak, D.L., Mounes-Toussi, F., Storino, S.N.

“…A 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a…”
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A 440-ps 64-bit adder in 1.5-V/0.18-[micro]m partially depleted SOI technology by Stasiak, D.L, Mounes-Toussi, F, Storino, S.N

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A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology by Stasiak, D.L., Mounes-Toussi, F., Storino, S.N.

“…A 64-bit adder in 1.5-V/0.18- mu m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-…”
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A 0.2-/spl mu/m, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects by Aipperspach, A.G., Allen, D.H., Cox, D.T., Phan, N.V., Storino, S.N.

“…A 550-MHz 64-b PowerPC processor in 0.2-um silicon-on-insulator (SOI) copper technology achieves a 22% frequency gain over a similar design in a CMOS bulk…”
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A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects by Aipperspach, A.G., Allen, D.H., Cox, D.T., Phan, N.V., Storino, S.N.

“…A 550-MHz 64-b PowerPC processor in 0.2-um silicon-on-insulator (SOI) copper technology achieves a 22% frequency gain over a similar design in a CMOS bulk…”
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A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor by Kuang, J.B., Buchholtz, T.C., Dance, S.M., Warnock, J.D., Storino, S.N., Wendel, D., Bradley, D.H.

“…The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a…”
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The design and implementation of double-precision multiplier in a first-generation CELL processor by Kuang, J.B., Buchholtz, T.C., Dance, S.M., Warnock, J.D., Storino, S.N., Wendel, D., Bradley, D.H.

“…We present the double precision multiplier for a 90nm PD-SOI first-generation CELL processor. Dynamic booth logic is designed for scalability and with noise,…”
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SOI implementation of a 64-bit adder by Tran, J.V., Mounes-Toussi, F., Storino, S.N., Stasiak, D.L.

“…Silicon-On-Insulator (SOI) technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel effect, and soft error…”
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A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects by Allen, D.H., Aipperspach, A.G., Cox, D.T., Phan, N.V., Storino, S.N.

“…A 64 b PowerPC RISC microprocessor is incorporated in a 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors and next into a…”
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A 660 MHz 64b SOI processor with Cu interconnects by Buchholtz, T.C., Aipperspach, G., Cox, D.T., Phan, N.V., Storino, S.N., Strom, J.D., Williams, R.R.

“…The 64b PowerPC RISC microprocessor previously described is migrated from a 0.22 /spl mu/m SOI technology to a 0.18 /spl mu/m SOI technology. Key features of…”
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