Search Results - "Stop, Russell"

A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Dillon, Chris, Puckett, Scott, Gray, Bryce, Speir, Carroll, Lanford, Jonathan, Brunsilius, Janet, Derounian, Peter R., Jeffries, Brad, Mehta, Ushma, McShea, Matthew, Stop, Russell

“…We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and…”
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A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration by Ali, A M A, Morgan, A, Dillon, C, Patterson, G, Puckett, S, Bhoraskar, P, Dinc, H, Hensley, M, Stop, R, Bardsley, S, Lattimore, D, Bray, J, Speir, C, Sneed, R

“…This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that…”
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A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration by Ali, A.M.A., Morgan, A., Dillon, C., Patterson, G., Puckett, S., Hensley, M., Stop, R., Bhoraskar, P., Bardsley, S., Lattimore, D., Bray, J., Speir, C., Sneed, R.

“…We present a 16b 250MS/S ADC that employs background calibration of the residue amplifier gain errors. It has an integrated input buffer and is fabricated on a…”
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A 14-bit 100-Msample/s subranging ADC by Moreland, C., Murden, F., Elliott, M., Young, J., Hensley, M., Stop, R.

“…This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage…”
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A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver] by Hensley, M., Speir, C., Stop, R., Behel, K., Moreland, C., Patterson, G., Kelly, D., Manglani, M., Elliott, M., Puckett, S., Young, J., Murden, F.

“…An integrated circuit is presented which receives an input IF frequency in the range of 70-300 MHz, and achieves 117 dB of dynamic range in a 200 kHz bandwidth…”
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