A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers

An Itanium® processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 47; no. 1; pp. 177 - 193
Main Authors:	Riedlinger, Reid, Arnold, Ron, Biro, Larry, Bowhill, B., Crop, J., Duda, K., Fetzer, E. S., Franza, O., Grutkowski, T., Little, C., Morganti, C., Moyer, G., Munch, A., Nagarajan, M., Parks, C., Poirier, C., Repasky, B., Roytman, E., Singh, T., Stefaniw, M. W.
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01-01-2012 Institute of Electrical and Electronics Engineers
Subjects:	Applied sciences Architectural memory ordering Arrays Clocks Design. Technologies. Operation analysis. Testing double error correction double error detection (SECDEC) Electronics Exact sciences and technology failure in thousands (FIT) first level data (FLD) First level instruction (FLI) home agent instruction buffer logic (IBL) instruction level parrallelism (ILP) integer execution unit (IEU) Integrated circuits Integrated circuits by function (including memories and processors) Intel scalable memory interconnect (SMI) Iron Itanium processor family last level cache (LLC) memory controller (MC) Microprocessors mid level data cache (MLD) mid level instruction cache (MLI) ordering CZQueue (OZQ) quick path interconnect (QPI) Radio frequency random logic synthesized and placed circuitry (RLS) regional clock buffer (RCB) register file (RF) Registers second level data TLB (DTB) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices single error correction small signal arrays (SSA) structured datapath (SDP) thermal design power (TDP) Transistors translation look-aside buffer (TLB) triple error detection (DECTED) register file (RF) Wireless telecommunication integer execution unit (IEU) Clock Itanium processor family translation look-aside buffer (TLB) instruction level parrallelism (ILP) Least squares method Ordering Copper Small signal double error correction Recursive algorithm Integer programming first level data (FLD) random logic synthesized and placed circuitry (RLS) Intel scalable memory interconnect (SMI) Error correction single error correction Processor Cache memory Small signal behavior triple error detection (DECTED) double error detection (SECDEC) second level data TLB (DTB) quick path interconnect (QPI) thermal design power (TDP) Implementation Complementary MOS technology regional clock buffer (RCB) memory controller (MC), mid level data cache (MLD) Architectural memory ordering home agent small signal arrays (SSA) Die failure in thousands (FIT) Linear programming Transistor Buffer system Failures structured datapath (SDP) Thread instruction buffer logic (IBL) Interconnection Integrated circuit First level instruction (FLI) Error detection mid level instruction cache (MLI), ordering CZQueue (OZQ) last level cache (LLC)
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Description
Summary:	An Itanium® processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of up to 45 GB/s.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2011.2167809