Search Results - "Städele, M."

Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results by Granzner, R., Polyakov, V.M., Schwierz, F., Kittler, M., Luyken, R.J., Rösner, W., Städele, M.

“…The dc behavior of single-gate and double-gate MOSFETs with gate lengths ranging from 5 to 100 nm is simulated using drift-diffusion, hydrodynamic, and Monte…”
Get full text

NVM based on FinFET device structures by Hofmann, F., Specht, M., Dorda, U., Kömmling, R., Dreeskornfeld, L., Kretz, J., Städele, M., Rösner, W., Risch, L.

“…High density data flash memories are essentially used in mobile applications. Flash devices have a small form factor, high storage density and low power…”
Get full text

Transport mechanisms in atomic-layer-deposited Al2O3 dielectrics by Specht, M., Städele, M., Jakschik, S., Schröder, U.

“…We analyze the field and temperature dependence of electron currents through atomic-layer-deposited thin (3.6–6 nm) sheets of Al2O3 which were annealed above…”
Get full text

Exact Kohn-Sham Exchange Potential in Semiconductors by Städele, M., Majewski, J. A., Vogl, P., Görling, A.

Get full text

Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime by Luyken, R.J., Schulz, T., Hartwich, J., Dreeskornfeld, L., Städele, M., Rösner, W.

“…Drift-diffusion simulations have been carried out to investigate the design space for n-channel fully depleted (FD) SOI transistors with undoped channels and…”
Get full text

Metallization of molecular hydrogen: predictions from exact-exchange calculations by Städele, M, Martin, R M

“…We study metallization of molecular hydrogen under pressure using exact-exchange (EXX) Kohn-Sham density-functional theory in order to avoid well-known…”
Get full text

Tunneling through Thin Oxides—New Insights from Microscopic Calculations by Städele, M, Tuttle, B, Fischer, B, Hess, K

“…In this paper, we summarize our recent efforts to analyze transmission probabilities of extremely thin SiO2 gate oxides using microscopic models of…”
Get full text

Full-Band Tunneling Currents in Nanometer-Scale MOS Structures by Sacconi, F., Di Carlo, A., Lugli, P., Städele, M.

“…Using quantum mechanical methods that include the full band structure of Si and SiO2 and a self-consistent potential, we study tunneling through ultrathin…”
Get full text

Influence of crystal orientation and body doping on trigate transistor performance by Landgraf, E., Rösner, W., Städele, M., Dreeskornfeld, L., Hartwich, J., Hofmann, F., Kretz, J., Lutz, T., Luyken, R.J., Schulz, T., Specht, M., Risch, L.

“…This work characterizes long channel trigate transistors with respect to the systematic influence of crystal orientation and body doping on performance issues…”
Get full text

Novel dual bit tri-gate charge trapping memory devices by Specht, M., Kommling, R., Hofmann, F., Klandzievski, V., Dreeskornfeld, L., Weber, W., Kretz, J., Landgraf, E., Schulz, T., Hartwich, J., Rosner, W., Stadele, M., Luyken, R.J., Reisinger, H., Graham, A., Hartmann, E., Risch, L.

“…Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first…”
Get full text

Full band approach to tunneling in MOS structures by Sacconi, F., Di Carlo, A., Lugli, P., Stadele, M., Jancu, J.-M.

“…Using atomistic quantum mechanical tight-binding (TB) methods that include the full band structure, we study electron tunneling through three-dimensional…”
Get full text

Stability and band offsets of polar GaN/SiC(001) and AlN/SiC(001) interfaces by Städele, M., Majewski, J. A., Vogl, P.

Get full text

Reduction of layout variations with stress-compensated hybrid STI fills: a comprehensive analysis by Stadele, M., Ilicali, G., Landgraf, E., Goldbach, M., Finsterbusch, S., Lindolf, J., Radecker, J., Uhlig, B.

“…Based on a detailed I-V analysis, 2D/3D process/device simulation, and inline wafer bow measurements, we have investigated a number of stress-induced layout…”
Get full text

Nanoscale FinFETs for low power applications by Rösner, W., Landgraf, E., Kretz, J., Dreeskornfeld, L., Schäfer, H., Städele, M., Schulz, T., Hofmann, F., Luyken, R.J., Specht, M., Hartwich, J., Pamler, W., Risch, L.

“…N and p channel FinFETs with fin widths in the range of 15–30 nm and gate lengths down to 20 nm have been processed using e-beam-lithography and nano-etching…”
Get full text

Multi-level p+ tri-gate SONOS NAND string arrays by Friederich, C., Specht, M., Lutz, T., Hofinann, F., Dreeskornfeld, L., Weber, W., Kretz, J., Melde, T., Rosner, W., Landgraf, E., Hartwich, J., Stadele, M., Risch, L., Richter, D.

“…Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated…”
Get full text

Fabrication of ultra-thin-film SOI transistors using the recessed channel concept by Dreeskornfeld, L., Hartwich, J., Hofmann, F., Kretz, J., Landgraf, E., Luyken, R.J., Rösner, W., Schröter, R., Schulz, T., Specht, M., Städele, M., Weber, W., Risch, L.

“…In this article, ultra-thin-film SOI transistors fabricated by locally recessing the channel regions are presented. SOI MOSFETs with ultra-thin channels offer…”
Get full text

Impact of technology parameters on device performance of UTB-SOI CMOS by Schulz, T., Pacha, C., Luyken, R.J., Städele, M., Hartwich, J., Dreeskornfeld, L., Landgraf, E., Kretz, J., Rösner, W., Specht, M., Hofmann, F., Risch, L.

“…Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm. In…”
Get full text

Resonant electron tunneling through defects in ultrathin SiO2 gate oxides in MOSFETs by Städele, M., Fischer, B., Tuttle, B.R., Hess, K.

Get full text

Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications by Specht, M., Kommling, R., Dreeskornfeld, L., Weber, W., Hofmann, F., Alvarez, D., Kretz, J., Luyken, R.J., Rosner, W., Reisinger, H., Landgraf, E., Schulz, T., Hartwich, J., Stadele, M., Klandievski, V., Hartmann, E., Risch, L.

“…Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated…”
Get full text

Perspectives of fully-depleted SOI transistors down to 20nm gate length by LUYKEN, R. J, STÄDELE, M, RÖSNER, W, SCHULZ, T, HARTWICH, J, DREESKORNFELD, L, RISCH, L

“…Device simulations have been carried out for n-channel fully depleted SOI transistors with undoped channels and single gates. Si body thickness, lateral…”
Get full text