Search Results - "Srinivasan, Viji"
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Exploiting approximate computing for deep learning acceleration
Published in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01-03-2018)“…Deep Neural Networks (DNNs) have emerged as a powerful and versatile set of techniques to address challenging artificial intelligence (AI) problems…”
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Integrated analysis of power and performance for pipelined microprocessors
Published in IEEE transactions on computers (01-08-2004)“…Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a…”
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A prefetch taxonomy
Published in IEEE transactions on computers (01-02-2004)“…The growing difference between processor and main memory cycle time demands the use of aggressive prefetch algorithms to reduce the effective memory access…”
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4
Message from the Program Chairs
Published in 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA) (01-02-2019)Get full text
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
Published in IEEE journal of solid-state circuits (18-10-2024)“…Discrete AI inference cards, operating under form-factor and system-defined peak power constraints, must serve diverse inference requests with widely varying…”
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Microarchitectural techniques for power gating of execution units
Published in International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design; 09-11 Aug. 2004 (01-01-2004)“…Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce…”
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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18-02-2024)“…The rapid emergence of AI models, specifically large language models (LLMs) requiring large amounts of compute, drives the need for dedicated AI inference…”
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Efficient scrub mechanisms for error-prone emerging memories
Published in IEEE International Symposium on High-Performance Comp Architecture (01-02-2012)“…Many memory cell technologies are being considered as possible replacements for DRAM and Flash technologies, both of which are nearing their scaling limits…”
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Invited: Accelerator design for deep learning training
Published in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) (01-06-2017)“…Deep Neural Networks (DNNs) have emerged as a powerful and versatile set of techniques showing successes on challenging artificial intelligence (AI) problems…”
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10
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators
Published in 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (01-03-2021)“…A prevalent challenge for Deep Learning (DL) accelerators is how they are programmed to sustain utilization without impacting end-user productivity. Little…”
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Optimizing pipelines for power and performance
Published in 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings (2002)“…During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver…”
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Leadership Training Program Course for Slum Women to Prepare Them to Run Nutrition Education Classes for Other Women in Their Neighbourhood
Published in Community Development Journal (1971)“…A training course about nutrition and immunization for the people of a poor section in Madras was developed by the Community Development project. It was felt…”
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LEADERSHIP TRAINING COURSE FOR SLUM WOMEN TO PREPARE THEM TO RUN NUTRITION EDUCATION CLASSES FOR OTHER WOMEN IN THEIR NEIGHBOURHOOD
Published in Community development journal (01-01-1971)“…An account of the experiences of "Nava Nirmana," a community welfare org in Madras, in establishing & conducting a training course designed to teach local…”
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14
Optimizing pipelines for power and performance
Published in Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture (18-11-2002)“…During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver…”
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Conference Proceeding