Search Results - "Srinivasa Rao, Vempati"

Chemical reaction impact on MHD natural convection flow through porous medium past an exponentially stretching sheet in presence of heat source/sink and viscous dissipation by Reddy, Nalivela Nagi, Rao, Vempati Srinivasa, Reddy, B Ravindra

“…This study investigates the viscous dissipation impact on free convection MHD flow through a porous medium over an exponentially stretching surface in presence…”
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Impact of porosity on two-dimensional unsteady MHD boundary layer heat and mass transfer stagnation point flow with radiation and viscous dissipation by Reddy, Yanala Dharmendar, Goud, Bejawada Shankar, Nalivela, Nagi Reddy, Rao, Vempati Srinivasa

“…The purpose of the present research is to examine the effect of porosity in the presence of radiation and viscous dissipation on two-dimensional unsteady MHD…”
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Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling by Bhattacharya, Surya, Rao, Vempati Srinivasa

“…Since the invention of the transistor, we have enjoyed tremendous impact of semiconductors on electronic systems. Transistor scaling has played a critical role…”
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Panel Warpage of Fan-Out Panel-Level Packaging Using RDL-First Technology by Che, Fa Xing, Yamamoto, Kazunori, Rao, Vempati Srinivasa, Sekhar, Vasarla Nagendra

“…In this study, fan-out panel-level packaging (FO-PLP) technology using a redistribution layer (RDL) first approach is demonstrated using a large glass panel as…”
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Casson fluid flow over a stretched surface with exponential permeability: Soret, Dufour and chemical reaction effects on MHD heat transmission by Manthramurthy, Prashanth, Vempati, Srinivasa Rao

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Study of Cu Pad Expansion with Surrounding Dielectrics for Hybrid Bonding by Cheemalamarri, Hemanth Kumar, Lir, Ji, Lee, Wen, Rao, Vempati Srinivasa, Singh, Navab

“…Copper/dielectric hybrid bonding technology is a key enabler for advanced chip-level (chip-to-chip, chip-to-wafer) or wafer-level (wafer-to-wafer)…”
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Low Thermal Budget Fine-pitch Cu/Dielectric Hybrid Bonding with Cu Microstructure Modifications by Cheemalamarri, Hemanth Kumar, Van Nhat Anh, Tran, Guan, Chen Gim, Lim, Meng Keong, Vempati, Srinivasa Rao, Singh, Navab

“…Advanced packaging featuring vertical integration has emerged as a crucial technology facilitating high performance, low power consumption, and compatibility…”
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Cu/Dielectric hybrid bonding among Glass and Si by Cheemalamarri, Hemanth Kumar, Sundaram, Arvind, Van Nhat Anh, Tran, Jae Ok, Yoo, Rao, Vempati Srinivasa, Singh, Navab

“…Chaplets and advanced packaging technologies play a pivotal role in meeting the diverse and demanding requirements of data-intensive workloads, by offering…”
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Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultrathin Device by Xiaowu Zhang, Rajoo, R., Selvanayagam, C. S., Kumar, A., Rao, V. S., Khan, N., Kripesh, V., Lau, J. H., Dim-Lee Kwong, Sundaram, V., Tummala, R. R.

“…Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous…”
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Development of Large RDL Interposer Package using RDL-first FOWLP Process by Ho, Soon Wee, Boon Soh, Siew, Lau, Boon Long, Hsiang-Yao, Hsiao, Rao, Vempati Srinivasa

“…In this work, an organic RDL interposer with large package size of 52 x 44 mm consisting of 12 embedded chiplets on a 60 x 60 mm organic substrate has been…”
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Cu Damascene Process on Temporary Bonded Wafers for Thin Chip Stacking using Cu-Cu Hybrid Bonding by Sekhar, Vasarla Nagendra, Kumar, Mishra Dileep, Lianto, Prayudi, Chong, Ser Choong, Rao, Vempati Srinivasa

“…Hybrid bonding is one of the innovative permanent bonding technologies that form dielectric-dielectric and metal-metal bonds, respectively. Hybrid bonding is…”
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Multi-Chip Stacked Memory Module Development using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications by Sekhar, Vasarla Nagendra, Kumar, Mishra Dileep, Tippabhotla, Sasi Kumar, Rao, B. S. S. Chandra, Daniel, Ismael Cereno, Chong, Ser Choong, Rao, Vempati Srinivasa

“…The present study focuses on multi-chip stacked memory module development, and it encompasses a comprehensive overview of critical aspects, key learnings,…”
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Process Challenges in Thin Wafers Fabrication with Double Side Hybrid Bond Pads for Chip Stacking by Kumar, Mishra Dileep, Nagendra Sekhar, Vasarla, Rao, B.S.S. Chandra, Choong Chong, Ser, Rao, Vempati Srinivasa

“…3D packaging with stacked dies is widely explored as a future advanced packaging technology for applications involving high-performance computing and High…”
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Defect evolution during through-silicon via copper electroplating and methods for robust void-free filling by Van Nhat Anh, Tran, Venkataraman, Nandini, Tao, Meng, Ya-Ching, Tseng, Xiangyu, Wang, King-Jien, Chui, Singh, Navab, Rao, Vempati Srinivasa

“…Void-free electroplating of copper in high-aspect ratio via structures is an important capability for achieving high-reliability through silicon vias (TSVs)…”
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Reliability Assessment of 2.5D Module using Chip to Wafer Hybrid Bonding by Chong, Ser Choong, Au Keng Yuen, Jason, Sekhar, Vasarla Nagendra, Cereno Daniel, Ismael, Kumar, Mishra Dileep, Srinivasa Rao, Vempati

“…Wafer to wafer hybrid bonding has been established to form fine pitch interconnections for high density I/O applications [1], [2]. However, this approach has…”
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Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications by Kumar, Mishra Dileep, Nagendra Sekhar, Vasarla, Choong, Chong Ser, Chandra Rao, B.S.S., Chui, King-Jien, Rao, Vempati Srinivasa

“…High-bandwidth memory (HBM) market is witnessing huge demand for high performance computing. Vertical/3D stacking of memory chips using hybrid bonding is a…”
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Polymer Dielectric Materials Evaluation for Hybrid Bonding Applications by Sekhar, Vasarla Nagendra, Fujiwara, Takenori, Araki, Hitoshi, Shoji, Yu, Jukei, Masaya, Nomura, Kota, Kumar, Mishra Dileep, Ser Choong, Chong, Rao, Vempati Srinivasa

“…Hybrid bonding is an emerging technology for advanced packaging and heterogeneous integration. In this work, Cu/polymer-based hybrid bonding is being evaluated…”
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Multiple slip effects on steady MHD flow past a non-isothermal stretching surface in presence of Soret, Dufour with suction/injection by Reddy, Nalivela Nagi, Reddy, Yanala Dharmendar, Rao, Vempati Srinivasa, Goud, B. Shankar, Nisar, Kottakkaran Sooppy

“…The main purpose of this work is to investigate the influence of multi slip implications on steady-state MHD fluid flow in the occurrence of Soret and Dufour…”
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Design, assembly and reliability of large die and fine-pitch Cu/low- k flip chip package by Ong, Yue Ying, Ho, Soon Wee, Vaidyanathan, Kripesh, Sekhar, Vasarla Nagendra, Jong, Ming Chinq, Yak Long, Samuel Lim, Wen Sheng, Vincent Lee, Wai, Leong Ching, Rao, Vempati Srinivasa, Ong, Jimmy, Ong, Xuefen, Zhang, Xiaowu, Seung, Yoon Uk, Lau, John H., Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Yanfeng, Zhang, Tan, Juan Boon, Sohn, Dong Kyun

“…This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump…”
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Development of 4 die stack module using Hybrid bonding approach by Chong, Ser Choong, Keng Yuen, Jason Au, Sekhar, Vasarla Nagendra, Daniel, Ismael Cereno, Rao, Vempati Srinivasa

“…Die stacking is commonly used in memory modules. Solder micro-bumps and through silicon via (TSVs) are common interconnects, and it may not viable or suitable…”
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