Search Results - "Sparso, Jens"

Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016 by Sparsø, Jens

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PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments by Jelcicova, Zuzana, Kasapaki, Evangelia, Andersson, Oskar, Sparso, Jens

“…Recurrent neural networks (RNNs) are well-suited for sequential tasks such as speech enhancement (SE). However, their performance comes with high-computational…”
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Comparing timed-division multiplexing and best-effort networks-on-chip by Sparsø, Jens, Damsgaard, Hans Jakob, Katsamanis, Dimitrios, Schoeberl, Martin

“…Best-effort (BE) networks-on-chips (NOCs) are usually preferred over time-division multiplexed (TDM) NOCs in multi-core platforms because they are…”
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A time-predictable open-source TTEthernet end-system by Kyriakakis, Eleftherios, Lund, Maja, Pezzarossa, Luca, Sparsø, Jens, Schoeberl, Martin

“…Cyber-physical systems deployed in areas like automotive, avionics, or industrial control are often distributed systems. The operation of such systems requires…”
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Using dynamic partial reconfiguration of FPGAs in real-Time systems by Pezzarossa, Luca, Kristensen, Andreas Toftegaard, Schoeberl, Martin, Sparsø, Jens

“…The use of hardware accelerators to implement computationally intensive tasks in real-time systems can lead to a reduction of the worst-case execution time…”
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Hardlock: Real-time multicore locking by Strøm, Tórur Biskopstø, Sparsø, Jens, Schoeberl, Martin

“…Multiple threads executing on a multicore processor often communicate via shared objects, allocated in main memory, and protected by locks. A lock itself is…”
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Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers by Kasapaki, Evangelia, SparsØ, Jens

“…In this paper we explore the use of asynchronous routers in a time-division-multiplexed (TDM) network-on-chip (NOC), Argo, that is being developed for a…”
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A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip by Sørensen, Rasmus Bo, Pezzarossa, Luca, Schoeberl, Martin, Sparsø, Jens

“…This paper presents a resource-efficient time-division multiplexing network interface of a network-on-chip intended for use in a multicore platform for hard…”
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An area-efficient network interface for a TDM-based Network-on-Chip by Sparso, Jens, Kasapaki, Evangelia, Schoeberl, Martin

“…Network interfaces (NIs) are used in multi-core systems where they connect processors, memories, and other IP-cores to a packet switched Network-on-Chip (NOC)…”
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Scratchpad Memories with Ownership by Schoeberl, Martin, Strom, Torur Biskopsto, Baris, Oktay, Sparso, Jens

“…A multicore processor for real-time systems needs a time-predictable way to communicate data between different threads running on different cores. Standard…”
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A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip by Bjerregaard, Tobias, Sparso, Jens

“…On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed…”
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A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip by Sorensen, Rasmus Bo, Sparso, Jens, Pedersen, Mark Ruvald, Hojgaard, Jaspur

“…This paper presents a metaheuristic scheduler for inter-processor communication in multi-processor platforms using time division multiplexed (TDM) networks on…”
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Message Passing on a Time-predictable Multicore Processor by Sorensen, Rasmus Bo, Puffitsch, Wolfgang, Schoeberl, Martin, Sparso, Jens

“…Real-time systems need time-predictable computing platforms. For a multicore processor to be time-predictable, communication between processor cores needs to…”
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Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend by Nielsen, S.F., Sparso, J., Madsen, J.

“…The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an…”
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Message from the Chairs - ASYNC 2012 by Sparso, Jens, Singh, Montek, Vivet, Pascal

“…For the third time, ASYNC is co-located with the ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2012). The two conferences are back-to-back, ASYNC…”
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Analytical derivation of traffic patterns in cache-coherent shared-memory systems by Stuart, Matthias B., Sparsø, Jens

“…► Synthesis of interconnect requires model of communication in an application. ► Gap exists between models of applications and models of communication. ►…”
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T-CREST: Time-predictable multi-core architecture for embedded systems by Schoeberl, Martin, Abbaspour, Sahar, Akesson, Benny, Audsley, Neil, Capasso, Raffaele, Garside, Jamie, Goossens, Kees, Goossens, Sven, Hansen, Scott, Heckmann, Reinhold, Hepp, Stefan, Huber, Benedikt, Jordan, Alexander, Kasapaki, Evangelia, Knoop, Jens, Li, Yonghui, Prokesch, Daniel, Puffitsch, Wolfgang, Puschner, Peter, Rocha, André, Silva, Cláudio, Sparsø, Jens, Tocchi, Alessandro

“…Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are…”
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Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid by Nielsen, L.S., Sparso, J.

“…This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design…”
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PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks by Jelcicova, Zuzana, Jones, Rasmus, Blix, David Thorn, Verhelst, Marian, Sparseo, Jens

“…This paper introduces two dynamic real-time pruning techniques PeakRNN and StatsRNN for reducing costly multiplications and memory accesses in recurrent neural…”
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A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method by Bjerregaard, Tobias, Stensgaard, Mikkel Bystrup, Sparsø, Jens

“…Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking…”
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