Search Results - "Spallek, R.G."
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1
Generating the trace qualification configuration for MCDS from a high level language
Published in 2009 Design, Automation & Test in Europe Conference & Exhibition (01-04-2009)“…This paper introduces a high level trace qualification language and compiler which enables the user defining analysis tasks efficiently and fully utilize the…”
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2
Mapping basic prefix computations to fast carry-chain structures
Published in 2009 International Conference on Field Programmable Logic and Applications (01-08-2009)“…Carry chains are a standard feature of modern FPGA architectures. They enable compact, regular and yet very fast implementations of the binary word addition…”
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Implementation of Architecture Concepts for Hardware Agent Systems
Published in 7th IEEE International Conference on Computer and Information Technology (CIT 2007) (01-10-2007)“…Requirements to implement future information processing systems are in particular flexibility, adaptability, and reliability. Agent systems which are known…”
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About catties and tokens: re-using adder circuits for arbitration
Published in IEEE Workshop on Signal Processing Systems Design and Implementation, 2005 (2005)“…This paper explores the analogies among the carry propagation within binary adders and the token passing within arbiter implementations. This analysis…”
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Modelling and simulating the selective epitaxial growth of silicon under consideration of anisotropic growth rates
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)“…This work presents a new model for the simulation of thin layer deposition and etching processes. Especially suited for the simulation of highly anisotropic…”
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A High-Level Language and Compiler to Configure the Multi-core Debug Solution (MCDS)
Published in 2009 First International Conference on Advances in System Testing and Validation Lifecycle (01-09-2009)“…With the rise of multi-core system-on-chips (SoC) debug adds new requirements and challenges to the system visibility and control. Complex on-chip trace and…”
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Improving code efficiency for reconfigurable VLIW processors
Published in Proceedings 16th International Parallel and Distributed Processing Symposium (2002)Get full text
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Design space exploration of coarse-grain reconfigurable DSPs
Published in 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) (2005)“…This work introduces a new digital signal processor (DSP) architecture concept, which provides increased instruction-level parallelism (ILP), flexibility and…”
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Formal verification for microprocessors with extendable instruction set
Published in Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors (2000)“…The correctness of processors is a key for their application. Although some verification methods were developed and successfully applied to conventional…”
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Simulation of small Si and GaAs devices
Published in [1987] NASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits (1987)“…There are some general aspects of device simulation discussed. Subsequently, 2D- and 3D-device simulators ZANAL, SEMICO and SIMBA, resprctively, as well as…”
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