Search Results - "Soumyanath, K"

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS by Pellerano, S., Palaskas, Y., Soumyanath, K.

“…This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on…”
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A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity by Paramesh, J., Bishop, R., Soumyanath, K., Allstot, D.J.

“…A fully integrated four-channel multi-antenna receiver intended for beamforming and spatial diversity applications is presented. It can also be used as a…”
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A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS by Walling, J.S., Lakdawala, H., Palaskas, Y., Ravi, A., Degani, O., Soumyanath, K., Allstot, D.J.

“…A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to…”
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A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion by Elmala, M., Paramesh, J., Soumyanath, K.

“…A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel…”
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A sub-130-nm conditional keeper technique by Alvandpour, A., Krishnamurthy, R.K., Soumyanath, K., Borkar, S.Y.

“…Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two…”
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A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process by Palaskas, Y., Taylor, S.S., Pellerano, S., Rippke, I., Bishop, R., Ravi, A., Lakdawala, H., Soumyanath, K.

“…This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a…”
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Desensitized CMOS Low-Noise Amplifiers by Banerjee, G., Soumyanath, K., Allstot, D.J.

“…The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power…”
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A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file by Krishnamurthy, R.K., Alvandpour, A., Balamurugan, G., Shanbhag, N.R., Soumyanath, K., Borkar, S.Y.

“…Describes a 256-word 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic…”
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A 130-nm 6-GHz 256x32 bit leakage-tolerant register file by Krishnamurthy, R.K., Alvandpour, Atila, Balamurugan, G., Shanbhag, R., Soumyanath, K., Borkar, S.Y.

“…Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic…”
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Low voltage techniques for sub 100nm CMOS, RF transceivers by Soumyanath, K.

“…Sub 100 nm CMOS provides high f/sub T/ and f/sub max/ devices that offer many advantages for RFIC design. However, these benefits come with the necessity of…”
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Measurement and modeling errors in noise parameters of scaled-CMOS devices by Banerjee, G., Soumyanath, K., Allstot, D.J.

“…Noise parameter measurements of submicrometer scaled-CMOS devices are error prone. These errors can propagate to a device model affecting the performance of…”
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A 32nm low power RF CMOS SOC technology featuring high-k/metal gate by VanDerVoorn, P, Agostinelli, M, Choi, S, Curello, G, Deshpande, H, El-Tanani, M A, Hafez, W, Jalan, U, Janbay, L, Kang, M, Koh, K, Komeyli, K, Lakdawala, H, Lin, J, Lindert, N, Mudanai, S, Park, J, Phoa, K, Rahman, A, Rizk, J, Rockford, L, Sacks, G, Soumyanath, K, Tashiro, H, Taylor, S, Tsai, C, Xu, H, Xu, J, Yang, L, Young, I, Yeh, J, Yip, J, Bai, P, Jan, C

“…A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low…”
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Accurate on-chip interconnect evaluation: a time-domain technique by Soumyanath, K., Borkar, S., Chunyan Zhou, Bloechel, B.A.

“…This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this…”
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Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends by Mathew, S.K., Krishnamurthy, R.K., Anders, M.A., Rios, R., Mistry, K.R., Soumyanath, K.

“…In this paper, we present: 1) design of a single-rail energy-efficient 64-b Han-Carlson ALU, operating at 482 ps in 1.5 V, 0.18- mu m bulk CMOS; 2) direct port…”
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5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS by Vangal, S, Anders, M.A, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J.W, Ye, Y, Somasekhar, D, Bloechel, B.A, Dermer, G.E, Krishnamurthy, R.K, Soumyanath, K, Mathew, S, Narendra, S.G, Stan, M.R, Thompson, S, De, V, Borkar, S

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Sub-500ps 64b ALUs in 0.18 mu m SOI/bulk CMOS: Design & scaling trends by Mathew, S, Krishnamurthy, R, Anders, M, Rios, R, Mistry, K, Soumyanath, K

“…An energy-efficient 64b ALU in 0.18 mu m bulk CMOS technology was designed. A silicon-on-insulator (SOI)-optimal redesign of the adder core was presented. The…”
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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, BA, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, GE, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
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A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop by Soumyanath, K, Anders, Mark, Mathew, Sanu, Bloechel, Brad, Thompson, Scott, Krishnamurthy, Ram, Borkar, Shekhar

“…A discussion on instruction-scheduler loop and a 6.5 GHz 130nm single-ended dynamic arithmetic logic unit (ALU) is presented. The instruction scheduler used in…”
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An analog scheme for fixed-point computation-Part II: Applications by Soumyanath, K., Borkar, V.S.

“…In a companion paper [see ibid., vol. 44, p. 351-4, 1997] we presented theoretical analysis of an analog network for fixed-point computation. This paper…”
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RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications by Jan, C.-H, Agostinelli, M, Deshpande, H, El-Tanani, M A, Hafez, W, Jalan, U, Janbay, L, Kang, M, Lakdawala, H, Lin, J, Lu, Y.-L, Mudanai, S, Park, J, Rahman, A, Rizk, J, Shin, W.-K, Soumyanath, K, Tashiro, H, Tsai, C, VanDerVoorn, P, Yeh, J.-Y, Bai, P

“…The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of…”
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