Search Results - "Sooryong Lee"
-
1
Adversarial Defect Detection in Semiconductor Manufacturing Process
Published in IEEE transactions on semiconductor manufacturing (01-08-2021)“…Detecting defects in the inspection stage of semiconductor manufacturing process is a crucial task to improve yield and productivity as well as wafer quality…”
Get full text
Journal Article -
2
REDO-random excitation and deterministic observation-first commercial experiment
Published in Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) (1999)“…For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective…”
Get full text
Conference Proceeding
-
3
A new ATPG algorithm to limit test set size and achieve multiple detections of all faults
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002 (2002)“…Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple…”
Get full text
Conference Proceeding -
4
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D
Published in Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) (2000)“…Predicting the final value of the defective part level after the application of a set of test vectors is not a simple problem. In order for the defective part…”
Get full text
Conference Proceeding -
5
Fortuitous detection and its impact on test set sizes using stuck-at and transition faults
Published in 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings (2002)“…During manufacture testing, the maximum number of test patterns that can be applied is limited by the available amount of tester memory. This paper…”
Get full text
Conference Proceeding -
6
A new ATPG algorithm to generate compact test sets which detect static and dynamic defects in VLSI circuits
“…Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduce the overall defective part level. However, multiple…”
Get full text
Dissertation -
7
A new ATPG algorithm to generate compact test sets which detect static and dynamic defects in VLSI circuits
Published 01-01-2003“…Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduce the overall defective part level. However, multiple…”
Get full text
Dissertation -
8
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies
Published in International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)“…If many potential defects exist at each site in an integrated circuit, then as the number of applied test patterns increases, the number of defects which…”
Get full text
Conference Proceeding -
9
Defect-oriented testing and defective-part-level prediction
Published in IEEE design & test of computers (01-01-2001)“…After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test…”
Get full text
Journal Article