Search Results - "Somasekhar, D"

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology by Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.

“…We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access…”
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Leakage control with efficient use of transistor stacks in single threshold CMOS by Johnson, M.C., Somasekhar, D., Lih-Yih Chiou, Roy, K.

“…The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can…”
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Models and algorithms for bounds on leakage in CMOS circuits by Johnson, M.C., Somasekhar, D., Roy, K.

“…Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold…”
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Process, Temperature, and Supply-Noise Tolerant 45 ~nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits by Khellah, M., Nam Sung Kim, Yibin Ye, Somasekhar, D., Karnik, T., Borkar, N., Pandya, G., Hamzaoglu, F., Coan, T., Yih Wang, Zhang, K., Webb, C., De, V.

“…This paper addresses the stability problem of diffusion-notch-free (DNF) SRAM cells used in dense last level caches (LLC). A DNF cell eliminates lithographic…”
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Differential current switch logic: a low power DCVS logic family by Somasekhar, D., Roy, K.

“…Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked…”
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Safe Trade - A Stock Recommender using Machine Learning Algorithms by Julian, Anitha, GaneshReddy, E, Reddy, V R Dikshit, Somasekhar, D V V

“…The business and financial sector currently controls the majority of the global economy, and stock market trading is a key activity there. The project uses…”
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A 6-GHz 16-kB L1 cache in a 100-nm dual-v t technology using a bitline leakage reduction (blr) technique by Yibin Ye, Khellah, M., Somasekhar, D., Farhang, A., De, V.

“…This work describes an aggressive SRAM cell configuration using dual-V/T/ and minimum channel length to achieve high performance. A bitline leakage reduction…”
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Skewed CMOS: noise-tolerant high-performance low-power static circuit family by Solomatnikov, A., Somasekhar, D., Sirisantana, N., Roy, K.

“…In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits…”
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A quad-polarization and frequency reconfigurable square ring slot loaded microstrip patch antenna for WLAN applications by Bharathi, Anantha, Lakshminarayana, Merugu, Somasekhar Rao, P.V.D.

“…In this paper, a novel polarization and frequency reconfigurable microstrip patch antenna which can switch between vertical and horizontal linear…”
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A novel single feed frequency and polarization reconfigurable microstrip patch antenna by Anantha, Bharathi, Merugu, Lakshminarayana, Somasekhar Rao, P.V.D.

“…In this paper, a novel single feed frequency and polarization reconfigurable microstrip patch antenna is presented. This antenna mainly comprises of a corner…”
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Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique by Narendra, S., Tschanz, J., Hofsheier, J., Bloechel, B., Vangal, S., Hoskote, Y., Tang, S., Somasekhar, D., Keshavarzi, A., Erraguntla, V., Dermer, G., Borkar, N., Borkar, S., De, V.

“…A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more…”
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LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family by Somasekhar, D., Roy, K.

“…This paper presents a low voltage differential current switch logic (LVDCSL) gate capable of achieving high performance for large fan-in gates. High fan-in is…”
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Bitline leakage equalization for sub-100nm caches by Alvandpour, A., Somasekhar, D., Krishnamurthy, R., De, V., Borkar, S., Svensson, C.

“…This paper describes a leakage-tolerant circuit technique for embedded sub-100nm SRAM's. The proposed 8-transistor memory cells inject identical leakage…”
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A 230-MHz half-bit level pipelined multiplier using true single-phase clocking by Somasekhar, D., Visvanathan, V.

“…An 8-bit*8-bit signed two's complement pipelined multiplier megacell implemented in 1.6- mu m single-poly, double-metal N-well CMOS is described. It is capable…”
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Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process by Somasekhar, D., Srinivasan, B., Pandya, G., Hamzaoglu, F., Khellah, M., Karnik, T., Zhang, K.

“…A multi-phase 1 GHz charge pump in 32 nm logic process demonstrates a compact area (159 × 42 ¿m 2 ) for boosting supply voltage from twice the threshold…”
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Accuracy Evaluation of Estimated Ionospheric Delay of GPS Signals Based on Klobuchar and IRI-2007 Models in Low Latitude Region by Swamy, K. C. T., Sarma, A. D., Srinivas, V. Satya, Kumar, P. Naveen, Rao, P. V. D. Somasekhar

“…The required positional accuracy of GPS is limited by several error sources. Among these, the predominant error source is the ionosphere, which introduces…”
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Skewed CMOS: Noise-immune high-performance low-power static circuit family by Solomatnikov, A., Somasekhar, D., Roy, K.

“…In this paper, we present a noise-immune high-performance static circuit family called skewed logic. Skewed logic circuits in comparison with Domino logic have…”
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Dynamic noise analysis in precharge-evaluate circuits by Somasekhar, Dinesh, Choi, Seung Hoon, Roy, Kaushik, Ye, Yibin, De, Vivek

“…A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of…”
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Direct Compare of Information Coded With Error-Correcting Codes by Wei Wu, Somasekhar, D., Shih-Lien Lu

“…There are situations in a computing system where incoming information needs to be compared with a piece of stored data to locate the matching entry, e.g.,…”
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Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays by Augustine, C, Raychowdhury, A, Somasekhar, D, Tschanz, J, Roy, K, De, V K

“…This paper presents a numerical analysis of four genres of STT-MTJ stacks. A comprehensive study based on critical memory performance metrics such as TMR, J C…”
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