Search Results - "Soh, Lip Kai"

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  1. 1
    An adjustable reset pulse phase frequency detector for phase locked loop

    An adjustable reset pulse phase frequency detector for phase locked loop by Lip-Kai Soh, Edwin, Y.-F.K.

    “…In this paper, an adjustable reset pulse phase frequency detector (PFD) for phase-locked loop (PLL) is proposed and analyzed. The proposed PFD adjust the width…”
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  2. 2
    A low-noise phase-locked loop with programmable gain VCO

    A low-noise phase-locked loop with programmable gain VCO by Lip-Kai Soh

    “…In this paper, a phase-locked loop (PLL) with programmable gain VCO is proposed and analyzed. The proposed design adjusts the gain of the VCO based on the…”
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  3. 3
    A 2.5-12.5Gbps interpolator-based clock and data recovery circuit for FPGA

    A 2.5-12.5Gbps interpolator-based clock and data recovery circuit for FPGA by Lip-Kai Soh, Wai-Tat Wong

    “…This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm…”
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  4. 4
    Programmable low-dithering-jitter interpolator-based CDR

    Programmable low-dithering-jitter interpolator-based CDR by Lip-Kai Soh, Wai-Tat Wong, Swee-Wah Lee, Chuan-Thim Khor

    “…This paper presents a methodology to determine the optimum filter settings for interpolator-based CDR. The proposed methodology quantifies the relationship…”
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  5. 5
    7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and −58dBc TX HD2

    7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and −58dBc TX HD2 by Yang, Wei, Hu, De Yong, Lam, Chun Kit, Cui, Ji Qing, Soh, Lip Kai, Song, De Cheng, Zhong, Xiao Wei, Hor, Hon Cheong, Heng, Chee Lee

    “…To facilitate the ubiquitous deployment of wireless sensors for Internet-of-Things (IoT) applications, highly integrated ultra-low-power (ULP) RF transceivers…”
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  6. 6
    A fast-lock delay-locked loop architecture with improved precharged PFD

    A fast-lock delay-locked loop architecture with improved precharged PFD by Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida

    “…In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase…”
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  7. 7
    Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

    Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector by Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida

    “…In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog…”
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