Search Results - "Smrčka, Aleš"
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Cultural Heritage Viability: An Example of Traditional Transport in Central Europe
Published in Muzeológia a kultúrne dedičstvo (01-01-2021)“…This paper focuses on traditional transport as a form of cultural heritage in Central Europe, looking at the modes of transport that are still viable today as…”
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Utilizing parametric systems for detection of pipeline hazards
Published in International journal on software tools for technology transfer (01-02-2022)“…The current stress on having a rapid development cycle for microprocessors featuring pipeline-based execution leads to a high demand of automated techniques…”
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HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems
Published in Electronic proceedings in theoretical computer science (13-12-2016)“…HADES is a fully automated verification tool for pipeline-based microprocessors that aims at flaws caused by improperly handled data hazards. It focuses on…”
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Towards an extensive set of criteria for safety and cyber-security evaluation of cyber-physical systems
Published in Open research Europe (2023)“…Verification and validation (V&V) are complex processes combining different approaches and incorporating many different methods including many activities…”
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Vltavané – tradice plaveckých spolků. Výstava ke 150. výročí spolku Vltavan Praha. Národopisné muzeum Národního muzea, Kinského zahrada, Praha, 18. 5. – 19. 9. 2021
Published in Ceský lid (01-01-2021)“…More than sixty years have passed since the last time timber was sailed on the Vltava in a bundled state for subsistence purposes. It might seem that this…”
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DIE BEDEUTUNG DES HEUS UND SEIN TRADITIONELLER TRANSPORT IM RIESENGEBIRGE
Published in Ceský lid (01-01-2014)“…Most of the inhabitants of Krkonoše made their living by agriculture, brought by the colonists from the Alps in the second half of the 16th century. A…”
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Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors
Published in 2014 15th International Microprocessor Test and Verification Workshop (01-12-2014)“…Implementation of a pipeline-based execution of instructions in purpose-specific microprocessors is an error prone task, which implies a need of proper…”
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Conference Proceeding -
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Enhancing Security of AI-Based Code Synthesis with GitHub Copilot via Cheap and Efficient Prompt-Engineering
Published 19-03-2024“…AI assistants for coding are on the rise. However one of the reasons developers and companies avoid harnessing their full potential is the questionable…”
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HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems
Published 15-12-2016“…EPTCS 233, 2016, pp. 87-93 HADES is a fully automated verification tool for pipeline-based microprocessors that aims at flaws caused by improperly handled data…”
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10
NetLoiter: A Tool for Automated Testing of Network Applications using Fault-injection
Published in 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) (01-06-2023)“…The reliability of a network is a crucial requirement for applications and systems such as IoT (Internet-of-Things), cloud-based solutions, client-server, or…”
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Conference Proceeding -
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The VALU3S ECSEL project: Verification and validation of automated systems safety and security
Published in Microprocessors and microsystems (01-11-2021)“…Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities, which led to the…”
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Verifying Concurrent Programs Using Contracts
Published in 2017 IEEE International Conference on Software Testing, Verification and Validation (ICST) (01-03-2017)“…The central notion of this paper is that of contracts for concurrency, allowing one to capture the expected atomicity of sequences of method or service calls…”
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Conference Proceeding -
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Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description
Published in 2012 13th International Workshop on Microprocessor Test and Verification (MTV) (01-12-2012)“…The paper proposes an automated approach with a formal basis designed for checking correspondence between an RTL implementation of a microprocessor and a…”
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Conference Proceeding