Search Results - "Smedes, T"

ESD testing of devices, ICs and systems by Smedes, T.

“…This tutorial discusses several ways of ESD testing for devices, ICs and systems. A good understanding of the methods and the physics is required for relating…”
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Pitfalls for CDM calibration procedures by Smedes, T., Polewski, M., van IJzerloo, A., Lefebvre, J.L., Dekker, M.

“…A product qualification gave very different results for CDM testing between three labs. This paper describes the investigation into the root cause of these…”
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Selecting an appropriate ESD protection for discrete RF power LDMOSTs by Smedes, T., de Boet, J., Rödle, T.

“…For ESD protections of RF Power MOSTs, V t1 lowering by the RF signal – due to the d V/d t effect – can seriously degrade the RF performance. The use of a…”
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Study and validation of a power-rail ESD clamp in BiCMOS process with a reduced temperature dependency of its leakage current by BARBIER, F, BLANC, F, LE GRONTEC, A, COLCLASER, R, SMEDES, T, JOHNSON, M, BARDY, S, DESCAMPS, P

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A case study of ESD failures at random levels: analysis, explanation and solution by WU, T, SMEDES, T, LOKKER, J. P, MEI, S-N, SLOTBOOM, J. W

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An analytical model for the Non-Quasi-Static small-signal behaviour of submicron MOSFETs by Smedes, T., Klaassen, F.M.

“…A new, analytical Non-Quasi-Static model, in terms of admittance parameters, for the small-signal behaviour of short channel MOSFETs is presented. The relevant…”
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The application of transmission line pulse testing for the ESD analysis of integrated circuits by Smedes, T, Velghe, R.M.D.A, Ruth, R.S, Huitsing, A.J

“…Transmission line pulse (TLP) testing is well known for device characterisation in ESD circumstances. In this paper TLP is applied to full-integrated circuits…”
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CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study by Abessolo-Bidzo, D., Smedes, T., Huitsing, A. J.

“…The electrostatic discharge (ESD) sensitivity of ICs with respect to the charged-device model (CDM) is strongly dependent on the IC package, the substrate…”
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Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress by Sowariraj, M.S.B., de Jong, P.C., Cora, S.M., Smedes, T., Mouthaan, A.J.T., Kuper, F.G.

“…In the CDM type of ESD, the IC is both the source and part of the discharge current path. To study the CDM performance of an IC, a full-chip circuit model that…”
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A simple design methodology for increased ESD robustness of CMOS core cells by Huitsing, A.J., Smedes, T., Schroder, H.-U.

“…Certain ESD failures are caused by the destruction of a single NMOST finger in a core cell. This can be avoided by making the NMOST fingers wide enough to…”
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Pitfalls for CDM calibration procedures : ADVANCES IN ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR ICs by SMEDES, T, POLEWSKI, M, IJZERLOO, A. Van, LEFEBVRE, J. L, DEKKER, M

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Pitfalls for CDM calibration procedures by Smedes, T, Polewski, M, van IJzerloo, A, Lefebvre, J L, Dekker, M

“…A product qualification gave very different results for CDM testing between 3 labs. This paper describes the investigation into the root cause of these…”
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Analysis of ESD fails in a 45 nm mixed signal SoC by Smedes, T.

“…The analysis of ESD qualification fails for a large IC is presented. With a careful procedure all fails are explained. Several failures are related to stress…”
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A charge and capacitance model for modern MOSFETs by Smedes, T, Klaassen, F M

“…A new physical, compact charge and capacitance model for long to submicron size MOSFETs is presented. It includes the important short channel effects and the…”
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Practical modeling of the effects of processing fluctuations on circuit behaviour by Smedes, T., Emonts, P.G.A.

“…We describe a tool to predict and analyze the effects of processing fluctuations on circuit behaviour. This tool enables the designer to optimize the…”
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Statistical modeling and circuit simulation for design for manufacturing by Smedes, T., Emonts, P.G.A.

“…A method to include effects of statistical fluctuations, inherent to the semiconductor manufacturing process, in circuit simulation models is presented. It…”
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Fast computation of substrate resistances in large circuits by van Genderen, A.J., van der Meijs, N.P., Smedes, T.

“…In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits…”
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Accurate interconnect modeling: Towards multi-million transistor chips as microwave circuits by van der Meijs, N.P., Smedes, T.

“…In this paper we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to…”
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Characterization methods to replicate EOS fails by Smedes, T., Christoforou, Y., Zhao, S.

“…Two methods are proposed to complement traditional TLP methods for characterization of devices and ICs for EOS. These are used to determine the power profile:…”
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Extraction of circuit models for substrate cross-talk by Smedes, T., van der Meijs, N. P., van Genderen, A. J.

“…An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. This paper…”
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