Search Results - "Sixth international symposium on quality electronic design (isqed'05)"

Modeling within-die spatial correlation effects for process-design co-optimization by Friedberg, P., Cao, Y., Cain, J., Wang, R., Rabaey, J., Spanos, C.

“…Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on…”
Get full text

Thermal-aware floorplanning using genetic algorithms by Hung, W.-L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T., Irwin, M.J.

“…In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly…”
Get full text

A new method for design of robust digital circuits by Patil, D., Yun, S., Kim, S.-J., Cheung, A., Horowitz, M., Boyd, S.

“…As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental…”
Get full text

Combining system level modeling with assertion based verification by Dahan, A., Geist, D., Gluhovsky, L., Pidan, D., Shapir, G., Wolfsthal, Y., Benalycherif, L., Kamidem, R., Lahbib, Y.

“…Assertion based verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A…”
Get full text

Shifting perspectives on DFM by Sawicki, J.

“…Summary form only given. There is one universal truth in terms of design for manufacturing (DFM) - DFM tools and disciplines have always existed. In micron…”
Get full text

Modeling and design of chip-package interface by Devgan, A., Daniel, L., Krauter, B., He, L.

“…Summary form only given. Signal integrity (SI) and power integrity are forecast to be paramount issues for future chip and package designs. Larger numbers of…”
Get full text

Enabling true design for manufacturability by Kibarian, J.

“…Summary form only given. Without any doubt, design-for-manufacturability (DFM) has been the hottest buzzword for the last couple of years. This is quite…”
Get full text

Recent progress and remaining challenges in pattern transfer technologies for advanced chip designs by Sinha, A.K.

“…Summary form only given. Even as Moore's law continues to drive "tiny technologies" through relentless scaling, the main technology driver for semiconductor…”
Get full text

Design of sub-90 nm circuits and design methodologies by Devgan, A., Puri, R., Sapatnaker, S., Karnik, T., Joshi, R.

“…Summary form only given. The tutorial discusses the design challenges of scaled CMOS circuits in sub-90 nm technologies and the design methodologies required…”
Get full text

Power-delay metrics revisited for 90 nm CMOS technology by Sengupta, D., Saleh, R.

“…Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more…”
Get full text

Dummy filling methods for reducing interconnect capacitance and number of fills by Kurokawa, A., Kanamoto, T., Ibe, T., Kasebe, A., Chang Wei Fong, Kage, T., Inoue, Y., Masuda, H.

“…In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect…”
Get full text

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models by Yuanzhong Zhou, Connerney, D., Carroll, R., Luk, T.

“…A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor…”
Get full text

Nanoelectronics: Evolution or Revolution?

Get full text

Welcome Notes

“…Presents the welcome message from the conference proceedings…”
Get full text

IP Creation and Use What Roadblocks are Ahead or it is Just Clear and Bumpy Road?

Get full text

Best Paper Award

“…The award winners and the titles of their award winning papers are listed…”
Get full text

Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders by Amelifard, B., Fallah, F., Pedram, M.

“…Based on the idea of sharing two adders used in the carry select adder (CSA), a new design of a low-power high-performance adder is presented. The new adder is…”
Get full text

Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET by Mukhopadhyay, S., Mahmoodi, H., Roy, K.

“…The double-gate (DG) transistor has emerged as the most promising device for nanoscale circuit design. Independent control of front and back gate in DG devices…”
Get full text

Statistical analysis of clock skew variation in H-tree structure by Hashimoto, M., Yamamoto, T., Onodera, H.

“…This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important…”
Get full text

Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations by Venkatraman, V., Burleson, W.

“…The paper presents a novel process-tolerant multi-level signaling system for on-chip interconnects. Novel multi-level driver and receiver designs are presented…”
Get full text