Search Results - "Siok Wei Lim"

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  1. 1

    A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs by Savoj, Jafar, Hsieh, Kenny Cheng-Hsiang, Fu-Tai An, Gong, Jason, Jay Im, Xuewen Jiang, Jose, Anup P., Kireev, Vassili, Siok-Wei Lim, Roldan, Arianne, Turker, Didem Z., Upadhyaya, Parag, Wu, Daniel, Ken Chang

    Published in IEEE journal of solid-state circuits (01-11-2013)
    “…This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques…”
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    Journal Article Conference Proceeding
  2. 2

    A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET by Upadhyaya, Parag, Poon, Chi Fung, Lim, Siok Wei, Cho, Junho, Roldan, Arianne, Zhang, Wenfeng, Namkoong, Jin, Pham, Toan, Xu, Bruce, Lin, Winson, Zhang, Hongtao, Narang, Nakul, Tan, Kee Hian, Zhang, Geoff, Frans, Yohan, Chang, Ken

    Published in IEEE journal of solid-state circuits (01-01-2019)
    “…The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is…”
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    Journal Article
  3. 3

    A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS by Kok Lim Chan, Kee Hian Tan, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Siok Wei Lim, Roldan, Arianne, Narang, Nakul, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang

    Published in IEEE journal of solid-state circuits (01-10-2017)
    “…This paper describes a 32.75-Gb/s voltage-mode transmitter (TX) with three-tap feed forward equalization that is fabricated in a 16-nm FinFET CMOS technology…”
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    Journal Article
  4. 4
  5. 5

    3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS by Upadhyaya, Parag, Savoj, Jafar, Fu-Tai An, Bekele, Ade, Jose, Anup, Xu, Bruce, Wu, Daniel, Turker, Didem, Aslanzadeh, Hesam, Hedayati, Hiva, Im, Jay, Siok-Wei Lim, Chen, Stanley, Toan Pham, Frans, Yohan, Ken Chang

    “…The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high…”
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    Conference Proceeding Journal Article
  6. 6

    A 112-GB/S PAM4 Transmitter in 16NM FinFET by KeeHian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Roldan, Arianne, Hongyuan Zhao, Narang, Nakul, Siok Wei Lim, Carey, Declan, Ambatipudi, Sai Lalith Chaitanya, Upadhyaya, Parag, Frans, Yohan, Chang, Ken

    Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)
    “…This work reports a 112-Gb/s low power voltage-mode transmitter (TX) with four-tap feed forward equalization (FFE), designed and fabricated in 16nm FinFET…”
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    Conference Proceeding
  7. 7

    A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS by Kok Lim Chan, Kee Hian Tan, Frans, Yohan, Jay Im, Upadhyaya, Parag, Siok Wei Lim, Roldan, Arianne, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang

    “…This paper describes the design of a highly flexible voltage-mode transmitter with 3-tap Feed Forward Equalization fabricated in a 16nm CMOS technology. The…”
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    Conference Proceeding