Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form larg...

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Bibliographic Details
Published in:	2015 45th European Solid State Device Research Conference (ESSDERC) pp. 238 - 241
Main Authors:	Hussin, Razaidi, Franco, Jacopo, Vanderheyden, Annelies, Vanhaeren, Danielle, Horiguchi, Naoto, Kaczer, Ben, Asenov, Asen, Gerrer, Louis, Ding, Jie, Wang, Liping, Amoroso, Salvatore M., Cheng, Binjie, Reid, Dave, Weckx, Pieter, Simicic, Marco
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-09-2015
Subjects:	Aging Degradation Integrated circuit modeling MOS devices Semiconductor process modeling Threshold voltage Transistors
Online Access:	Get full text
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Summary:	This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.
ISBN:	9781467371339 1467371335
ISSN:	1930-8876
DOI:	10.1109/ESSDERC.2015.7324758