Search Results - "Simicic, M."

Hydrogen absorption and electrochemical properties of Mg2Ni-type alloys synthesized by mechanical alloying by SIMICIC, M. V, ZDUJIC, M, DIMITRIJEVIC, R, NIKOLIC-BUJANOVIC, Lj, POPOVIC, N. H

“…Mg2Ni-type alloys, i.e., Mg2Ni, Mg2Ni0.75Cu0.25, Mg2Ni0.6Cu0.4 and Mg2Ni0.75V0.25 were synthesized by mechanical alloying and subsequent thermal treatment…”
Get full text

Statistical Characterization of BTI and RTN using Integrated pMOS Arrays by Stampfer, B., Simicic, M., Weckx, P., Abbasi, A., Kaczer, B., Grasser, T., Waltl, M.

“…To study charge trapping kinetics of oxide and interface defects, BTI and RTN measurements are typically performed. However, characterizing and investigating a…”
Get full text

Advanced MOSFET variability and reliability characterization array by Simicic, M., Putcha, V., Parvais, B., Weckx, P., Kaczer, B., Groeseneken, G., Gielen, G., Linten, D., Thean, A.

“…Time-zero variability, bias temperature instability (BTI) and random telegraph noise (RTN) are issues that both analog and digital designers using scaled CMOS…”
Get full text

Characterization and simulation methodology for time-dependent variability in advanced technologies by Weckx, P., Kaczer, B., Raghavan, P., Franco, J., Simicic, M., Roussel, Ph J., Linten, D., Thean, A., Verkest, D., Catthoor, F., Groeseneken, G.

“…This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield…”
Get full text

Comphy — A compact-physics framework for unified modeling of BTI by Rzepa, G., Franco, J., O’Sullivan, B., Subirats, A., Simicic, M., Hellings, G., Weckx, P., Jech, M., Knobloch, T., Waltl, M., Roussel, P.J., Linten, D., Kaczer, B., Grasser, T.

“…Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research,…”
Get full text

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability by Kaczer, B., Franco, J., Weckx, P., Roussel, Ph.J., Putcha, V., Bury, E., Simicic, M., Chasin, A., Linten, D., Parvais, B., Catthoor, F., Rzepa, G., Waltl, M., Grasser, T.

“…A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels…”
Get full text

Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology by Lin, S.-H., Simicic, M., Pantano, N., Chen, S.-H., Van Der Plas, G., Beyne, E., Wambacq, P.

“…This paper presents a methodology to help prevent overdesign of Electrostatic Discharge (ESD) protection circuits for internal I/O in 2.5D/3D bonding…”
Get full text

The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits by Kaczer, B., Franco, J., Weckx, P., Roussel, Ph.J., Simicic, M., Putcha, V., Bury, E., Cho, M., Degraeve, R., Linten, D., Groeseneken, G., Debacker, P., Parvais, B., Raghavan, P., Catthoor, F., Rzepa, G., Waltl, M., Goes, W., Grasser, T.

“…As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability…”
Get full text

External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options by Chen, W.-C., Chen, S.-H., Hellings, G., Bury, E., Simicic, M., Wu, Z., Van der Plas, G., Groeseneken, G., Beyne, E.

“…In this paper, the challenges of the I/O development roadmap are discussed. The impact of I/O application in FEOL scaling and 3D integration are evaluated. A…”
Get full text

Statistical assessment of the full VG/VD degradation space using dedicated device arrays by Bury, E., Kaczer, B., Chuang, K., Franco, J., Weckx, P., Chasin, A., Simicic, M., Linten, D., Groeseneken, G.

“…Variability of as-fabricated (i.e., time-zero) parameters of modern VLSI devices has been considered in circuit design tools for some time. Also work on…”
Get full text

Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology by Hellings, G., Mertens, H., Subirats, A., Simoen, E., Schram, T., Ragnarsson, L.-A., Simicic, M., Chen, S.-H., Parvais, B., Boudier, D., Cretu, B., Machillot, J., Pena, V., Sun, S., Yoshida, N., Kim, N., Mocuta, A., Linten, D., Horiguchi, N.

“…This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW)…”
Get full text

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies by Chen, S.-H., Linten, D., Hellings, G., Simicic, M., Kaczer, B., Chiarella, T., Mertens, H., Mitard, J., Mocuta, A., Horiguchi, N.

“…Voltage transient overshoot is an essential device characteristic of ESD protection diodes under CDM-like stress. Using 3D TCAD and vfTLP characterization, the…”
Get full text

Defect-based compact modeling for RTN and BTI variability by Weckx, P., Simicic, M., Nomoto, K., Ono, M., Parvais, B., Kaczer, B., Raghavan, P., Linten, D., Sawada, K., Ammo, H., Yamakawa, S., Spessot, A., Verkest, D., Mocuta, Anda

“…This paper describes a defect-centric based compact modeling methodology for time-dependent threshold voltage variability (V TH ), induced by Bias Temperature…”
Get full text

Self-heating-aware CMOS reliability characterization using degradation maps by Bury, E., Chasin, A., Kaczer, B., Chuang, K.-H., Franco, J., Simicic, M., Weckx, P., Linten, D.

“…Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier…”
Get full text

Scaling CMOS beyond Si FinFET: an analog/RF perspective by Parvais, B., Hellings, G., Simicic, M., Weckx, P., Mitard, J., Jang, D., Deshpande, V., van Liempc, B., Veloso, A., Vandooren, A., Waldron, N., Wambacq, P., Collaert, N., Verkest, D.

“…FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the…”
Get full text

Benchmarking time-dependent variability of junctionless nanowire FETs by Kaczer, B., Rzepa, G., Franco, J., Weckx, P., Chasin, A., Putcha, V., Bury, E., Simicic, M., Roussel, Ph, Hellings, G., Veloso, A., Matagne, Ph, Grasser, T., Linten, D.

“…Time-dependent variability of junctionless gate-all-around nanowire pFETs is studied through measurements and simulations. The variability, related to effects…”
Get full text

A fully-integrated method for RTN parameter extraction by Simicic, M., Morrison, S., Parvais, B., Weckx, P., Kaczer, B., Sawada, K., Ammo, H., Yamakawa, S., Nomoto, K., Ohno, M., Linten, D., Verkest, D., Wambacq, P., Groeseneken, G., Gielen, G.

“…A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN…”
Get full text

Experimental evidences and simulations of trap generation along a percolation path by Gerrer, Louis, Hussin, Razaidi, Amoroso, Salvatore M., Franco, J., Weckx, P., Simicic, M., Horiguchi, N., Kaczer, Ben, Grasser, T., Asenov, Asen

“…In this paper we present experimental results of single trap impact on bulk MOSFETs, shedding light on counter intuitive behavior when increasing the gate…”
Get full text

Hydrogen storage material based on LaNi5 alloy produced by mechanical alloying by SIMICIC, M. V, ZDUJIC, M, JELOVAC, D. M, RAKIN, P. M

Get full text

An experimental study of zinc morphology in alkaline electrolyte at low direct and pulsating overpotentials by Simičić, M.V., Popov, K.I., Krstajić, N.V.

“…A possible mechanism of the formation of spongy zinc electrodeposits is considered. The confirmation of the proposed semiquantitative mathematical model is…”
Get full text