Search Results - "Silberman, Joel"

Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology by Xiaoxiong Gu, Silberman, Joel A., Young, Albert M., Jenkins, Keith A., Dang, Bing, Yong Liu, Xiaomin Duan, Gordin, Rachel, Shlafman, Shlomo, Goren, David

“…Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and…”
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A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias by Wordeman, M., Silberman, J., Maier, G., Scheuermann, M.

“…3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache…”
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Efficient AI System Design With Cross-Layer Approximate Computing by Venkataramani, Swagath, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Choi, Jungwook, Kang, Mingu, Agarwal, Ankur, Oh, Jinwook, Jain, Shubham, Babinsky, Tina, Cao, Nianzheng, Fox, Thomas, Fleischer, Bruce, Gristede, George, Guillorn, Michael, Haynie, Howard, Inoue, Hiroshi, Ishizaki, Kazuaki, Klaiber, Michael, Lo, Shih-Hsien, Maier, Gary, Mueller, Silvia, Scheuermann, Michael, Ogawa, Eri, Schaal, Marcel, Serrano, Mauricio, Silberman, Joel, Vezyrtzis, Christos, Wang, Wei, Yee, Fanchieh, Zhang, Jintao, Ziegler, Matthew, Zhou, Ching, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Srinivasan, Vijayalakshmi, Chang, Leland, Gopalakrishnan, Kailash

“…Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered…”
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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling by Lee, Sae Kyu, Agrawal, Ankur, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia M., Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Kar, Monodeep, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael R., Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm…”
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey K., Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Rower, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…Discrete AI inference cards, operating under form-factor and system-defined peak power constraints, must serve diverse inference requests with widely varying…”
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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference by Venkataramani, Swagath, Srinivasan, Vijayalakshmi, Wang, Wei, Sen, Sanchari, Zhang, Jintao, Agrawal, Ankur, Kar, Monodeep, Jain, Shubham, Mannari, Alberto, Tran, Hoang, Li, Yulong, Ogawa, Eri, Ishizaki, Kazuaki, Inoue, Hiroshi, Schaal, Marcel, Serrano, Mauricio, Choi, Jungwook, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Allain, Allison, Bonano, James, Cao, Nianzheng, Casatuta, Robert, Cohen, Matthew, Fleischer, Bruce, Guillorn, Michael, Haynie, Howard, Jung, Jinwook, Kang, Mingu, Kim, Kyu-hyoun, Koswatta, Siyu, Lee, Saekyu, Lutz, Martin, Mueller, Silvia, Oh, Jinwook, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Schelm, Kerstin, Scheuermann, Michael, Silberman, Joel, Yang, Jie, Zalani, Vidhi, Zhang, Xin, Zhou, Ching, Ziegler, Matt, Shah, Vinay, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their…”
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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey, Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Roewer, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…The rapid emergence of AI models, specifically large language models (LLMs) requiring large amounts of compute, drives the need for dedicated AI inference…”
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Designing for a gigahertz [guTS integer processor] by Hofstee, H.P., Sang H. Dhong, Meltzer, D., Nowka, K.J., Silberman, J.A., Burns, J.I., Posluszny, S.D., Takahashi, O.

“…At the IEEE International Solid State Circuits Conference this February, the IBM Austin Research Laboratory presented an experimental 64-bit integer processor…”
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A Scalable Multi-TeraOPS Core for AI Training and Inference by Shukla, Sunil, Fleischer, Bruce, Ziegler, Matthew, Silberman, Joel, Oh, Jinwook, Srinivasan, Vijayalakshmi, Choi, Jungwook, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Cao, Nianzheng, Chen, Chia-Yu, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Lee, Dongsoo, Lo, Shih-Hsien, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Wang, Naigang, Yee, Fanchieh, Zhou, Ching, Lu, Pong-Fei, Curran, Brian, Chang, Leland, Gopalakrishnan, Kailash

“…This letter presents a multi-TOPS AI accelerator core for deep learning training and inference. With a programmable architecture and custom ISA, this engine…”
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9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling by Agrawal, Ankur, Lee, Sae Kyu, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia, Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kar, Monodeep, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael, Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…Low-precision computation is the key enabling factor to achieve high compute densities (TOPS/W and TOPS/mm 2 ) in AI hardware accelerators across cloud and…”
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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference by Fleischer, Bruce, Shukla, Sunil, Ziegler, Matthew, Silberman, Joel, Jinwook Oh, Srinivasan, Vijavalakshmi, Jungwook Choi, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Nianzheng Cao, Chia-Yu Chen, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Dongsoo Lee, Shih-Hsien Lo, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Curran, Brian, Lel Chang, Gopalakrishnan, Kailash

“…A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable…”
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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference by Oh, Jinwook, Lee, Sae Kyu, Kang, Mingu, Ziegler, Matthew, Silberman, Joel, Agrawal, Ankur, Venkataramani, Swagath, Fleischer, Bruce, Guillorn, Michael, Choi, Jungwook, Wang, Wei, Mueller, Silvia, Ben-Yehuda, Shimon, Bonanno, James, Cao, Nianzheng, Casatuta, Robert, Chen, Chia-Yu, Cohen, Matt, Erez, Ophir, Fox, Thomas, Gristede, George, Haynie, Howard, Ivanov, Vicktoria, Koswatta, Siyu, Lo, Shih-Hsien, Lutz, Martin, Maier, Gary, Mesh, Alex, Nustov, Yevgeny, Rider, Scot, Schaal, Marcel, Scheuermann, Michael, Sun, Xiao, Wang, Naigang, Yee, Fanchieh, Zhou, Ching, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…A processor core is presented for AI training and inference products. Leading-edge compute efficiency is achieved for robust fp16 training via efficient…”
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(HgCd)Te–SiO2 interface structure by Wilson, J. A., Cotton, V. A., Silberman, Joel, Laser, D., Spicer, W. E., Morgen, P.

“…Low‐temperature chemical vapor deposited (CVD) SiO2 has proven to be a very important material for use as a passivation on HgCdTe, principally because it…”
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Power-conscious design of the Cell processor's synergistic processor element by Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Silberman, J.

“…The authors describe the low-power design of the synergistic processor element (SPE) of the cell processor developed by Sony, Toshiba and IBM. CMOS static…”
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Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor by Asano, T., Silberman, J., Dhong, S.H., Takahashi, O., White, M., Cottier, S., Nakazato, T., Kawasumi, A., Yoshihara, H.

“…The synergistic processor element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a…”
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A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor by Dhong, S.H., Takahashi, O., White, M., Asano, T., Nakazato, T., Silberman, J., Kawasumi, A., Yoshihara, H.

“…A 6-stage fully pipelined embedded SRAM is implemented in a 90nm SOI technology. The array uses a conventional 6-transistor memory cell and sense amplifier to…”
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A 1.0-GHz single-issue 64-bit powerPC integer processor by Silberman, J., Aoki, N., Boerstler, D., Burns, J.L., Sang Dhong, Essbaum, A., Ghoshal, U., Heidel, D., Hofstee, P., Kyung Tek Lee, Meltzer, D., Hung Ngo, Nowka, K., Posluszny, S., Takahashi, O., Vo, I., Zoric, B.

“…The organization and circuit design of a 1.0 GHz integer processor built in 0.25 /spl mu/m CMOS technology are presented, a microarchitecture emphasizing…”
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Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts by Xiaoxiong Gu, Silberman, J., Yong Liu, Xiaomin Duan

“…Substrate noise coupling induced by Through Silicon Vias in SOI substrates is modeled and analyzed in frequency- and time-domain. In addition to a buried oxide…”
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3D integration ESD protection design and analysis by Mitra, Souvick, Gebreselasie, Ephrem, You Li, Gauthier, Robert, Silberman, Joel, Tyberg, Christy, Sakuma, Katsuyuki, Thuy Tran-Quinn, Ramachandran, Koushik, Angyal, Matthew

“…A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection…”
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A shorted global clock design for multi-GHz 3D stacked chips by Liang-Teck Pang, Restle, P. J., Wordeman, M. R., Silberman, J. A., Franch, R. L., Maier, G. W.

“…A global clock distribution technique for 3D stacked chips where the clock tree and grid are shorted between strata is presented and compared with a DLL-based…”
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