Search Results - "Siegwart, H"
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Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors
Published in Applied physics letters (06-02-2012)“…Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001)…”
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Journal Article -
2
Direct observation of the alignment of ferromagnetic spins by antiferromagnetic spins
Published in Nature (London) (15-06-2000)“…The arrangement of spins at interfaces in a layered magnetic material often has an important effect on the properties of the material. One example of this is…”
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3
Towards large size substrates for III-V co-integration made by direct wafer bonding on Si
Published in APL materials (01-08-2014)“…We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V…”
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4
CMOS compatible self-aligned S/D regions for implant-free InGaAs MOSFETs
Published in Solid-state electronics (01-08-2012)“…► S/D access regions for self-aligned implant-free InGaAs MOSFETs are investigated. ► A combination of in situ dopped raised InGaAs S/D with Nickel–InGaAs…”
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5
Observation of Antiferromagnetic Domains in Epitaxial Thin Films
Published in Science (American Association for the Advancement of Science) (11-02-2000)“…Antiferromagnetic domains in an epitaxial thin film, LaFeO3on SrTiO3(100), were observed using a high-spatial-resolution photoelectron emission microscope with…”
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6
SrHfO3 as gate dielectric for future CMOS technology
Published in Microelectronic engineering (01-09-2007)“…Thin epitaxial films of the high-kappa perovskite SrHfO3 were grown by molecular beam epitaxy on Si(100) and investigated by ellipsometry and X-ray…”
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Conference Proceeding Journal Article -
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An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01-06-2015)“…We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique…”
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Conference Proceeding Journal Article -
8
Interface formation and defect structures in epitaxial La2Zr2O7 thin films on (111) Si
Published in Applied physics letters (22-12-2003)“…We have studied the growth of epitaxial La2Zr2O7 thin films on (111) Si. Although the interface structure can be strongly affected by the Si oxidation during…”
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9
Heterointegration by molecular beam epitaxy: (In,Ga)As/GaAs quantum wells on GaAs, Ge, Ge/Si and Ge/Si pillars
Published in Journal of crystal growth (01-09-2013)“…(In,Ga)As/GaAs quantum wells were heterogeneously integrated on planar and patterned Ge/Si (001) substrates by molecular beam epitaxy. Both nominal and vicinal…”
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Journal Article Conference Proceeding -
10
GaAs on 200 mm Si wafers via thin temperature graded Ge buffers by molecular beam epitaxy
Published in Journal of crystal growth (15-05-2011)“…For heterogeneous integration of III-V compound materials on 200 mm Si wafers, we present a complete in-situ molecular beam epitaxy (MBE) process from a Ge…”
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Conference Proceeding Journal Article -
11
1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs
Published in Microelectronic engineering (01-07-2011)“…The formation of low- k Hf silicate in a-Si passivated gate stacks on GaAs has been identified as the limiting factor in reaching the 1 nm CET as required for…”
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Journal Article Conference Proceeding -
12
Phase of reflection high-energy electron diffraction oscillations during (Ba,Sr)O epitaxy on Si(100): A marker of Sr barrier integrity
Published in Applied physics letters (26-12-2005)“…We use the reflection high-energy electron diffraction oscillation phase shift to monitor the stability of the Sr barrier, prepared by exposure of Si(100) to…”
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13
Lanthanum germanate as dielectric for scaled Germanium metal–oxide–semiconductor devices
Published in Microelectronic engineering (01-07-2009)“…We report a study of La 2O 3 with lanthanum germanate (LGO) as interfacial layer, or LGO alone as a gate dielectric candidate for scaled germanium…”
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Journal Article Conference Proceeding -
14
Co-integrating high mobility channels for future CMOS, from substrate to circuits
Published in 26th International Conference on Indium Phosphide and Related Materials (IPRM) (01-05-2014)“…Direct wafer bonding can be a vehicle for the dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. Like for SiGe, direct wafer bonding…”
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Conference Proceeding -
15
In-situ MBE Si as passivating interlayer on GaAs for HfO2 MOSCAP’s: effect of GaAs surface reconstruction
Published in Microelectronic engineering (01-09-2007)“…We report a study of MOS capacitors having a dielectric of HfO2 and an interlayer of Si deposited in-situ, by MBE on GaAs surfaces prepared with various…”
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Journal Article -
16
III/V layer growth on Si and Ge surfaces for direct wafer bonding as a path for hybrid CMOS
Published in 2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) (01-06-2014)“…As Si-CMOS scaling has become increasingly challenging, III-V compound semiconductors such as In x Ga 1-x As (x≥0.53) (InGaAs) are receiving much interest as…”
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Conference Proceeding -
17
Field-effect transistors with SrHfO3 as gate oxide
Published in Applied physics letters (31-07-2006)“…The authors demonstrate that the compound SrHfO3 grown epitaxially on Si(100) by molecular-beam epitaxy is a potential gate dielectric to fabricate n- and…”
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18
Sub-nm equivalent oxide thickness on Si-passivated GaAs capacitors with low Dit
Published in Applied physics letters (01-08-2011)“…A thin amorphous silicon interlayer, inserted between the III-V semiconductor and the gate dielectric is expected to prevent III-V oxidation, as required for…”
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Journal Article -
19
Sub-nm equivalent oxide thickness on Si-passivated GaAs capacitors with low D it
Published in Applied physics letters (01-08-2011)“…A thin amorphous silicon interlayer, inserted between the III-V semiconductor and the gate dielectric is expected to prevent III-V oxidation, as required for…”
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Journal Article -
20
Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In 0.53 Ga 0.47 As metal-oxide-semiconductor field-effect-transistors
Published in Applied physics letters (08-02-2012)“…Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2nm HfO 2 /1nm Al 2 O 3 /1nm a-Si gate stacks on p-In 0.53 Ga 0.47 As/InP…”
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Journal Article