Search Results - "Siah, S.Y."

STT-MRAM Product Reliability and Cross-Talk by Naik, V. B., Yamane, K., Kwon, J., Lim, J.H., Balasankaran, N., Chung, N.L., Hau, L.Y., Chao, R., Chiang, C., Huang, Y., Pu, L., Ma, L., Meng, C., Otani, Y., Zhang, L., Jang, S.H., Ling, T., Ting, J.W., Yoon, H., Mueller, J., Pfefferling, B., Kallensee, O., Merbeth, T., Seet, C.S., Wong, J., You, Y.S., Soss, S., Chan, T.H., Siah, S.Y.

“…STT-MRAM has been showcased to be a viable solution to replace eFlash and SRAM technologies. With the increasing demand for connected edge computing and…”
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The role of a tensile stress bias for a sensitive silicon mechanical stress sensor based on a change in gate-induced-drain leakage current by Lau, W.S., Yang, Peizhen, Siah, S.Y., Chan, L.

“…Mechanical stress sensors based on silicon piezoresistance have limited sensitivity. Mechanical stress sensors based on the on-current or off-current or…”
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Effects of switching from 〈110〉 to 〈100〉 channel orientation and tensile stress on n-channel and p-channel metal–oxide-semiconductor transistors by Yang, Peizhen, Lau, W.S., Lai, Seow Wei, Lo, V.L., Siah, S.Y., Chan, L.

“…We investigate the effects of switching from 〈110〉 to 〈100〉 channel orientation on NMOS and PMOS transistors. For NMOS transistors, we have experimentally…”
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Drain current saturation at high drain voltage due to pinch off instead of velocity saturation in sub-100nm metal–oxide–semiconductor transistors by Lau, W.S., Yang, Peizhen, Chian, Jason Zhiwei, Ho, V., Loh, C.H., Siah, S.Y., Chan, L.

“…Older MOS transistor theory pointed out that drain current saturation is due to pinch off for MOS transistors with large gate length and due to velocity…”
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A study of the linearity between Ion and logIoff of modern MOS transistors and its application to stress engineering by Lau, W.S., Yang, Peizhen, Eng, C.W., Ho, V., Loh, C.H., Siah, S.Y., Vigar, D., Chan, L.

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A study of the linearity between I on and log I off of modern MOS transistors and its application to stress engineering by Lau, W.S., Yang, Peizhen, Eng, C.W., Ho, V., Loh, C.H., Siah, S.Y., Vigar, D., Chan, L.

“…The authors observed that the on-current ( I on) and the logarithm of the off-current (log( I off)) of modern submicron MOS transistors tend to follow a very…”
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Selection of gate length and gate bias to make nanoscale metal–oxide-semiconductor transistors less sensitive to both statistical gate length variation and temperature variation by Yang, Peizhen, Lau, W.S., Lai, Seow Wei, Lo, V.L., Siah, S.Y., Chan, L.

“…Aggressive scaling of transistors leads to an ever-increasing amount of process variations. In this work, we studied the gate length dependency of on-current (…”
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Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors by Lau, W.S., Yang, Peizhen, Lim, Eng Hua, Tang, Yee Ling, Lai, Seow Wei, Lo, V.L., Siah, S.Y., Chan, L.

“…The merging of halo implants from the drain side and the source side creates a maximum in the magnitude of the threshold voltage and thus a minimum in the…”
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An explanation of the dependence of the effective saturation velocity on gate voltage in sub-0.1 μm metal–oxide–semiconductor transistors by quasi-ballistic transport theory by Lau, W.S., Yang, Peizhen, Ho, V., Toh, L.F., Liu, Y., Siah, S.Y., Chan, L.

“…In 1992, Takagi and Toriumi reported that the electron saturation velocities decrease with the density of inversion charge in metal–oxide–semiconductor…”
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40nm Embedded Self-Aligned Split-Gate Flash Technology for High-Density Automotive Microcontrollers by Shum, Danny, Luo, Lai Q., Kong, Y.J., Deng, F.X., Qu, X., Teo, Z.Q., Liu, J. Q., Zhang, F., Cai, X.S., Tan, K.M., Lim, K.Y., Khoo, P., Yeo, P.Y., Nguyen, B.Y., Jung, S.M., Siah, S.Y., Pey, K.L., Shubhakar, K., Wang, C.M., Xing, J.C., Liu, G.Y., Diao, Y., Lin, G.M., Luo, F., Tee, L., Markov, V., Lemke, S.M., Ghazavi, P., Do, Nhan, Tiwari, Vipin, Liu, Xian

“…This paper successfully demonstrates a logic-compatible, high performance and high reliability, automotive-grade 2.5V embedded NVM process extending over…”
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Void formation in titanium desilicide/p + silicon interface: impact on junction leakage and silicide sheet resistance by Pey, K.L, Sundaresan, R, Wong, H, Siah, S.Y, Tung, C.H

“…We have observed the formation of voids at the interface of TiSi 2/p +-Si after the titanium-salicidation process in a deep-sub-micron CMOS technology. In our…”
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Effects of high current conduction in sub-micron Ti-silicided films by Gan, C.L., Pey, K.L., Chim, W.K., Siah, S.Y.

“…Modeling and characterization of high current conduction in sub-micron titanium disilicide (TiSi 2) films formed on n +/p + silicon and n +/p + polysilicon…”
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Effective channel length increased due to switching from ≪110≫ to ≪100≫ orientation for PMOS transistors fabricated by 65 nm CMOS technology by Lau, W.S., Peizhen Yang, Ho, V., Lim, B.K., Siah, S.Y., Chan, L.

“…The on-state current of PMOS transistors fabricated on (100) Si substrate can be easily increased by switching from to orientation because of faster hole…”
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Region of nearly constant off current versus gate length characteristics for sub-0.1 μm low power CMOS technology by Lau, W.S., Peizhen Yang, Ng, E.T.L., Chian, Z.W., Ho, V., Siah, S.Y., Chan, L.

“…A minimum in the off current versus gate length characteristics can occur at a threshold voltage maximum for MOS transistors. Sometimes, instead of a minimum,…”
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A comparison between the quasi-ballistic transport model and the conventional velocity saturation model for sub-0.1-μm mos transistors by Peizhen Yang, Lau, W.S., Ho, V., Loh, C.H., Siah, S.Y., Chan, L.

“…Conventional velocity saturation model does not explain why mobility enhancement through stress engineering can improve the on-current of sub-0.1 μm…”
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A mechanism of increase in the on-current and offcurrent due to a slightly smaller spacer in state-of- the-art p-channel MOS transistors during manufacturing by Lau, W.S., Eng, C.W., Tee, K.M., Siah, S.Y., Vigar, D., Kim, Y.T., Lal, M., Bhat, M., Chan, L.

“…Our observation is that both the oncurrent and off-current of state-of- the-art pchannel MOS transistors tend to become larger when the spacer becomes smaller…”
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Impact of voids in Ti-salicided p/sup +/ polysilicon lines on TiSi/sub 2/ electrical properties by Chua, H.N., Pey, K.L., Siah, S.Y., Ong, L.Y., Lim, E.H., Gan, C.L., See, K.H., Ho, C.S.

“…We report the effect of voids in Ti-salicided narrow p/sup +/-doped polysilicon lines on the electrical performance of the TiSi/sub 2/ films. The variation in…”
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Correlation of film thickness and deposition temperature with PAI and the scalability of Ti-salicide technology to sub-0.18 /spl mu/m regime by Ho, C.S., Karunasiri, R.P.G., Chua, S.J., Pey, K.L., Siah, S.Y., Lee, K.H., Chan, L.H.

“…We present the first working solutions for a sub-0.25 /spl mu/m Ti-salicide process incorporating /sup 14/Si or Ar/sup +/ PAI (preamorphization implant)…”
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