Search Results - "Shirota, R"

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  1. 1

    Dominant expansion of a cryptic subclone with an abnormal karyotype in B lymphoblastoid cell lines during culture by Danjoh, I, Shirota, R, Hiroyama, T, Nakamura, Y

    Published in Cytogenetic and genome research (2013)
    “…Although B lymphoblastoid cell lines (B-LCLs) are thought to maintain their original genomic structures during long-term culture, there has been considerable…”
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    Journal Article
  2. 2

    Reliability issues of flash memory cells by Aritome, S., Shirota, R., Hemink, G., Endoh, T., Masuoka, F.

    Published in Proceedings of the IEEE (01-05-1993)
    “…Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash…”
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    Journal Article
  3. 3

    Productivity and economics of Nile tilapia Oreochromis niloticus cage culture in South-East Brazil by Conte, L, Sonoda, D.Y, Shirota, R, Cyrino, J.E.P

    Published in Journal of applied aquaculture (2008)
    “…Fish cage culture is an intensive, continuous-flow fish farming system, allowing intensive exploitation of water bodies with relatively low capital investment…”
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    Journal Article
  4. 4

    A compact on-chip ECC for low cost flash memories by Tanzawa, T., Tanaka, T., Takeuchi, K., Shirota, R., Aritome, S., Watanabe, H., Hemink, G., Shimizu, K., Sato, S., Takeuchi, Y., Ohuchi, K.

    Published in IEEE journal of solid-state circuits (01-05-1997)
    “…A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells,…”
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    Journal Article
  5. 5

    A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory by Tanaka, T., Tanaka, Y., Nakamura, H., Sakui, K., Oodaira, H., Shirota, R., Ohuchi, K., Masuoka, F., Hara, H.

    Published in IEEE journal of solid-state circuits (01-11-1994)
    “…This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The…”
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    Journal Article
  6. 6

    Test and repair of non-volatile commodity and embedded memories (NAND flash memory) by Shirota, R.

    “…Summary form only given. The test time of the memory chip is a very important issue. It mainly depends on the program and erase time. NAND flash memories…”
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    Conference Proceeding
  7. 7

    Ranching and the new global range: Amazônia in the 21st century by Walker, Robert, Browder, John, Arima, Eugenio, Simmons, Cynthia, Pereira, Ritaumaria, Caldas, Marcellus, Shirota, Ricardo, Zen, Sergio de

    Published in Geoforum (01-09-2009)
    “…This paper seeks to understand how the Brazilian Amazon, which many thought unsuitable for agricultural development, has yielded to a dynamic cattle economy in…”
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    Journal Article
  8. 8

    Analytical Model to Evaluate the Role of Deep Trap State in the Reliability of NAND Flash Memory and Its Process Dependence by Yang, B-J, Wu, Y-T, Chiu, Y-Y, Shirota, R., Kuo, T-M, Chang, J-H, Wang, P-Y

    “…An elementary step of trap and detrap processes of electron in the tunnel oxide during program/erase in NAND Flash memory is precisely studied. Owing to the…”
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    Conference Proceeding
  9. 9

    A side-wall transfer-transistor cell (SWATT cell) for highly reliable multi-level NAND EEPROMs by Aritome, S., Takeuchi, Y., Sato, S., Watanabe, I., Shimizu, K., Hemink, G., Shirota, R.

    Published in IEEE transactions on electron devices (01-01-1997)
    “…A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost…”
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    Journal Article
  10. 10

    An accurate model of subbreakdown due to band-to-band tunneling and some applications by Endoh, T., Shirota, R., Momodomi, M., Masuoka, F.

    Published in IEEE transactions on electron devices (01-01-1990)
    “…An accurate model and a numerical analysis of the subbreakdown phenomenon due to band-to-band tunneling in a thin-gate-oxide n-MOSFET is described. Results…”
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  11. 11

    Scaling trend of the Flash memory for file storage by Shirota, R.

    “…This paper describes the review of flash memory. First, the fundamental device and design characteristics of flash memory are shown. Next, recent developments…”
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    Conference Proceeding
  12. 12

    Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction by Watanabe, H, Aritome, S, Hemink, G J, Maruyama, T, Shirota, R

    “…Through the use of a lower impurity concentration in the gate poly-Si and lowering the post-annealing temperature, a highly reliable tunnel oxide…”
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    Journal Article
  13. 13

    A New Programming Scheme for the Improvement of Program Disturb Characteristics in Scaled nand Flash Memory by Shirota, R., Chen-Hao Huang, Nagai, S., Sakamoto, Y., Fu-Hai Li, Mitiukhina, N., Arakawa, H.

    Published in IEEE transactions on electron devices (01-10-2012)
    “…This paper investigates the new programming scheme to reduce the program disturb in the NAND Flash memory. Program disturb characteristics are determined by…”
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    Journal Article
  14. 14

    Roadmap of the Flash Memory by Shirota, R.

    “…It has become 19 years, since the development of the NAND Flash started using 0.7..m rule in 1987. The speed of the scaling has been very fast and the period…”
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    Conference Proceeding
  15. 15

    Analysis of the Correlation Between the Programmed Threshold-Voltage Distribution Spread of nand Flash Memory Devices and Floating-Gate Impurity Concentration by Shirota, R., Sakamoto, Y., Hung-Ming Hsueh, Jian-Ming Jaw, Wen-Chuan Chao, Chih-Ming Chao, Sheng-Fu Yang, Arakawa, H.

    Published in IEEE transactions on electron devices (01-11-2011)
    “…The effect of the activated floating-gate (FG) impurity concentration on the programmed threshold-voltage ( V t ) distribution was newly investigated and…”
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    Journal Article
  16. 16

    An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell by Momodomi, M., Itoh, Y., Shirota, R., Iwata, Y., Nakayama, R., Kirisawa, R., Tanaka, T., Aritome, S., Endoh, T., Ohuchi, K., Masuoka, F.

    Published in IEEE journal of solid-state circuits (01-10-1989)
    “…A 5-V-only high-density (512 K*8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a…”
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    Journal Article
  17. 17

    Self-aligned shallow trench isolation recess effect on cell performance and reliability of 42nm NAND flash memory by Liu, C H, Lin, Y M, Shirota, R, Wei, H C, Kuo, L T, Liu, C Han, Chen, S H, Hwang, H P, Sakamoto, Y, Pittikoun, S

    “…Self-aligned shallow trench isolation recess effect on 42 nm node NAND flash to achieve high performance and good reliability has been studied and…”
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    Conference Proceeding
  18. 18

    A high-density NAND EEPROM with block-page programming for microcomputer applications by Iwata, Y., Momodomi, M., Tanaka, T., Oodaira, H., Itoh, Y., Nakayama, R., Kirisawa, R., Aritome, S., Endoh, T., Shirota, R., Ohuchi, K., Masuoka, F.

    Published in IEEE journal of solid-state circuits (01-04-1990)
    “…A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is…”
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    Journal Article
  19. 19

    Impact of Edge Encroachment on Programming and Erasing Gate Current in nand -Type Flash Memory by Ji-Ting Liang, Chun-Hsing Shih, Wei Chang, Yan-Xiang Luo, Ming-Kun Huang, Nguyen Dang Chien, Wen-Fa Wu, Sau-Mou Wu, Chenhsin Lien, Shirota, R, Chiu-Tsung Huang, Su Lu, Wang, A

    Published in IEEE transactions on electron devices (01-04-2011)
    “…The edge encroachment of tunnel oxide is experimentally found to degrade the Fowler-Nordheim (FN) tunneling gate current of NAND-type Flash cells. This work…”
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    Journal Article
  20. 20

    Improvement of oxide reliability in NAND flash memories using tight endurance cycling with shorter idling period by Shirota, R., Yang, B.-J, Chiu, Y.-Y, Wu, Y.-T, Wang, P.-Y, Chang, J.-H, Yano, M., Aoki, M., Takeshita, T., Wang, C.-Y, Kurachi, I.

    “…It has been newly found that shorter intervals between program and erase operations can suppress the oxide degradation more significantly in a 0.05 to 5 sec…”
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    Conference Proceeding