Search Results - "Shim, Da Eun"

Impact of Technology Scaling and Back-end-of-the-line Technology Solutions on Magnetic Random-Access Memories by Kumar, Piyush, Shim, Da Eun, Narla, Siri, Naeemi, Azad

“…While magnetic random-access memories (MRAMs) are promising thanks to their non-volatility, relatively fast speeds, and high endurance, there are major…”
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A Comprehensive Modeling Platform for Interconnect Technologies by Shim, Da Eun, Huang, Victor, Chen, Xinkang, Gupta, Sumeet K., Naeemi, Azad

“…With device scaling facing major physical and manufacturing challenges, many research efforts have been focused on the impact of device parameters and designs…”
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FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction by Asgari, Bahar, Hadidi, Ramyad, Cao, Jiashen, Shim, Da Eun, Lim, Sung-Kyu, Kim, Hyesoon

“…Memory-bound sparse gathering, caused by irregular random memory accesses, has become an obstacle in several on-demand applications such as embedding lookup in…”
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A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology by Pentapati, Sai, Zhu, Lingjun, Bamberg, Lennart, Shim, Da Eun, Garcia-Ortiz, Alberto, Lim, Sung Kyu

“…In recent years, the size of transistors has been scaled down to a few nanometers and further shrinking will eventually reach the atomic scale. Monolithic…”
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A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications by Agnesina, Anthony, Shim, Da Eun, Yamaguchi, James, Krutzik, Christian, Carson, John, Nakamura, Dan, Lim, Sung Kyu

“…In this work, we develop a new 3D flash memory cube architecture that integrates multiple flash dies and their logic controller in a unique and optimized…”
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Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs by Bamberg, Lennart, Garcia-Ortiz, Alberto, Zhu, Lingjun, Pentapati, Sai, Shim, Da Eun, Kyu Lim, Sung

“…Memory-on-logic and sensor-on-logic face-to-face stacking are emerging design approaches that promise a significant increase in the performance of modern…”
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Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs by Shim, Da Eun, Pentapati, Sai, Lee, Jeehyun, Yu, Yun Seop, Kyu Lim, Sung

“…In this paper, we propose simple but effective clock tree optimization algorithms for monolithic 3D ICs that are based on tier partitioning and flip-flop…”
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FLASHRAD: A Reliable 3D Rad Hard Flash Memory Cube Utilizing COTS for Space by Shim, Da Eun, Sidana, Amanvir Singh, Yamaguchi, Jim S., Krutzik, Christian, Nakamura, Dan, Lim, Sung Kyu

“…Given the rapid rate of growth and scope for space missions, improving computing capabilities of onboard spacecraft and memory systems is vital for future…”
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Balancing Interconnect Resistance and Capacitance at the Advanced Technology Nodes based on Full Chip Analysis by Shim, Da Eun, Naeemi, Azad

“…This paper presents a technology-circuit cooptimization flow to achieve the best balance between wire resistance and capacitance in advanced technology nodes…”
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Signal-Power Interconnect Co-Design Based on Various Technology Options by Shim, Da Eun, Kini, Akshata Ashok, Mallikarjuna, Meghana, Kumar, Piyush, Naeemi, Azad

“…While the impact of various BEOL improvements on circuit-level PPA has been well studied, their implications for PDNs have not been properly explored. This…”
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Exploring FinFET and Gate-All-Around FET for SRAM Cell Arrays at the 3 nm Process Node by Bush, Bennett, Mack, Jacob, Hanks, Luke, Collector, Trinity, Cai, Zhuoqi, Naeemi, Azad, Shim, Da Eun

“…Improving transistor performance is increasingly challenging as technology nodes continue to scale, putting pressure on the limitations of the current…”
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Improving SRAM Performance With Different Interconnect Options at the 7 nm Process Node by Mack, Jacob, Datta, Rudranshu, Young, Brandon, Cai, Zhuoqi, Naeemi, Azad, Shim, Da Eun

“…Modern-day technology node scaling trends have exacerbated interconnect resistance and capacitance problems in chips. The ultra-narrowing wires that result in…”
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Modeling and Benchmarking Back End Of The Line Technologies on Circuit Designs at Advanced Nodes by Huang, Victor, Shim, Da Eun, Kim, Jinwoo, Pentapati, Sai, Lim, Sung Kyu, Naeemi, Azad

“…Interconnect scaling has become an ever-growing challenge as the industry advances to ever smaller nodes. In this work we present a comprehensive framework to…”
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LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference for IoT by Hadidi, Ramyad, Asgari, Bahar, Cao, Jiashen, Bae, Younmin, Shim, Da Eun, Kim, Hyojong, Lim, Sung-Kyu, Ryoo, Michael S., Kim, Hyesoon

“…Deep neural networks (DNNs) have stimulated research in diverse edge applications including robotics and Internet-of-Things (IoT) devices. However, IoT-based…”
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Vortex: OpenCL Compatible RISC-V GPGPU by Elsabbagh, Fares, Tine, Blaise, Roshan, Priyadarshini, Lyons, Ethan, Kim, Euna, Shim, Da Eun, Zhu, Lingjun, Lim, Sung Kyu, kim, Hyesoon

“…The current challenges in technology scaling are pushing the semiconductor industry towards hardware specialization, creating a proliferation of heterogeneous…”
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Hot Chips 2020 Posters by Elsabbagh, Fares, Tine, Blaise, Chawda, Apurve, Gulian, Will, Feng, Yaotian, Shim, Da Eun, Roshan, Priyadarshini, Lyons, Ethan, Zhu, Lingjun, Lim, Sung Kyu, Kim, Hyesoon

“…The emergence of data parallel architectures have enabled new opportunities to address the power limitations and scalability of multi-core processors, allowing…”
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LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference in Image Recognition by Hadidi, Ramyad, Asgari, Bahar, Cao, Jiashen, Bae, Younmin, Shim, Da Eun, Kim, Hyojong, Lim, Sung-Kyu, Ryoo, Michael S, Kim, Hyesoon

“…Deep neural networks (DNNs) have inspired new studies in myriad edge applications with robots, autonomous agents, and Internet-of-things (IoT) devices…”
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