Search Results - "Sheu, Gene"

A Novel Nitrogen Ion Implantation Technique for Turning Thin Film “Normally On” AlGaN/GaN Transistor into “Normally Off” Using TCAD Simulation by Sheu, Gene, Song, Yu-Lin, Susmitha, Dupati, Issac, Kutagulla, Mogarala, Ramyasri

“…This study presents an innovative, low-cost, mass-manufacturable ion implantation technique for converting thin film normally on AlGaN/GaN devices into…”
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Breakdown Behavior of Metal Contact Positions in GaN HEMT with Nitrogen-Implanted Gate Using TCAD Simulation by Sheu, Gene, Song, Yu-Lin, Mogarala, Ramyasri, Susmitha, Dupati, Issac, Kutagulla

“…In this study, the breakdown behavior of a calibrated depletion mode AlGaN/GaN transistor with a nitrogen-implanted gate region was simulated and analyzed…”
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Physics-Based TCAD Simulation and Calibration of 600 V GaN/AlGaN/GaN Device Characteristics and Analysis of Interface Traps by Song, Yu-Lin, Reddy, Manoj Kumar, Chang, Luh-Maan, Sheu, Gene

“…This study proposes an analysis of the physics-based TCAD (Technology Computer-Aided Design) simulation procedure for GaN/AlGaN/GaN HEMT (High Electron…”
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120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process by Deivasigamani, Ravi, Sheu, Gene, Aryadeep, Chirag, Sai, S. Krishna, Selvendran, S., Yang, Shao-Ming

“…In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is…”
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Analysis of Anti-JFET for 600V VDMOS and HCI Reliability by Yang, Shao-Ming, Sheu, Gene, Lai, Chiu-Chung, Deivasigamani, Ravi

“…In VDMOS device the anti-JFET concentration has important role for determining the breakdown voltage and on-resistance of the device. Because higher N-drift…”
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Sensitivity Study of Polysilicon Nanowire Based on Scattering and Quantum Mechanics Models by Aanand, Sheu, Gene, Imam, Syed Sarwar, Lu, Shao Wei, Yang, Shao-Ming, Fan, Ming Jen

“…In this paper, we report nanowire drain saturation current sensitivity property to measure femtomol level change in drain current due to different proteins…”
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Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology by Yang, Shao-Ming, Sheu, Gene, Lee, Tzu Chieh, Chien, Ting Yao, Wu, Chieh Chih, Lin, Yun Jung

“…High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and…”
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Study of HCI Reliability for PLDMOS by Deivasigamani, Ravi, Sheu, Gene, Aanand, Wei Lu, Shao, Sarwar Imam, Syed, Lai, Chiu-Chung, Yang, Shao-Ming

“…In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat…”
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An Innovated 80V-100V High-Side Side-Isolated N-LDMOS Device by Yangi, Shao Ming, Sheu, Gene, Chien, Ting Yao, Wu, Chieh Chih, Lee, Tzu Chieh, Wu, Ching Yuan, Lai, Chiu Chung

“…We used TCAD Synopsys 3D tools and device simulators to propose an innovative device structure of 80V-100V high-side NLDMOS by using the silicon to…”
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Gate Engineering in SOI LDMOS for Device Reliability by Aanand, Sheu, Gene, Imam, Syed Sarwar, Lu, Shao Wei, Aryadeep, Chirag, Yang, Shao Ming

“…A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF) SOI LDMOS transistor performance has…”
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Study of impact of LATID on HCI reliability for LDMOS devices by Chandrashekhar, Sheu, Gene, Yang, Shao Mingo, Chien, Ting Yao, Lin, Yun Jung, Wu, Chieh Chih, Lee, Tzu Chieh

“…This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation…”
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An Analytical Model of Surface Electric Field Distributions in Ultrahigh-Voltage Buried P-Top Lateral Diffused Metal--Oxide--Semiconductor Devices by Sheu, Gene, Yang, Shao-Ming, Chang, Yi-Fong, Tsaur, Shyh Chang

“…In this paper, we present an analytical model for determining surface electric field distributions in buried P-top lateral-diffused metal--oxide--semiconductor…”
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Analysis of Kirk effect of an innovated high side Side-Isolated N-LDMOS device by Lai, Ciou Jhong, Sheu, Gene, Chien, Ting Yao, Wu, Chieh Chih, Lee, Tzu Chieh, Deivasigamani, Ravi, Wu, Ching Yuan, Chandrashekhar, Yang, Shao Ming

“…An ESOA of LDMOS device is very critical for power device performance. Kirk effect is the one of the major problem which leads to poor ESOA performance. The…”
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A study of low cost 1200V linear P-top LDMOS device by Gene Sheu, Ching-Yi Huang

“…In this paper, low cost 1200V UHV LDMOS device has been proposed. As BVD and Ron are contradictory, so to make low Ron, high breakdown voltage is the challenge…”
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An innovated JFET structure to adjust the pinch-off voltage by using a control gate by Gene Sheu, Ming-Che Yang, Ching-Yuan Wu

“…A novel N-JFET structure, combined with an innovative control gate between the uniform P-top and source is proposed. Control gate has a heavily doped P-type…”
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An analysis of doping concentration profile for UHV LDMOS linear P-Top by Gene Sheu, Imam, Syed Neyaz, Ming-Che Yang, Deshmane, Pooja, Bharti, Monika

“…This paper presents the effect of side diffusion and doping concentration profile produced by two different ion implantation model for UHV LDMOS device with…”
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Investigation of ruggedness failure and UIS performance improvement by using drain engineering technique in UHV-JFET by Jaiswal, Suman, Gene Sheu, Ming-Che Yang, Imam, Syed Neyaz, Po-An Chen

“…This paper investigates the failure mechanism of Ultra High Voltage JFET (UHV-JFET) under Unclamped Inductive Switching (UIS) test. We explain the ruggedness…”
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Design for hot-carrier reliability of HV UMOS by Aryadeep, Chirag, Gene Sheu, Selvendran, Sivaji, Jaiswal, Suman, Krishna Sai, S., Mastanbasheer, Shaik, Sai Dheeraj, Muntha, Po-An Chen

“…An innovative and improved UMOS device structure, with gate oxide 900 to 1500A, breakdown voltage 40 to 100V, robust to hot carrier injection (HCI) stress is…”
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DNA Biosensor Applications for Poly-Silicon Nanowire Field-Effect Transistors by Shao-Wei Lu, Chia-Hsien Li, Aanand, Imam, Syed Sarwar, Shao-Ming Yang, Ming-Jen Fan, Gene Sheu

“…In this paper, a normal nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary…”
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A study of interstitial effect on UMOS performance by Hema, E. P., Gene Sheu, Aryadeep, M., Yang, S. M.

“…Threshold voltage shift is a major problem for UMOS device. This study explains how device performance can be affected by silicon defects (interstitial and…”
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