Search Results - "Sherony, M"

Coworker Exchange: Relationships Between Coworkers, Leader-Member Exchange, and Work Attitudes by Sherony, Kathryn M, Green, Stephen G

“…The study of leadership exchanges is extended by studying both leader-member exchanges (LMXs) and coworker exchanges (CWXs). Data from 110 coworker dyads were…”
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SOI MOSFET effective channel mobility by Sherony, M.J., Su, L.T., Chung, J.E., Antoniadis, D.A.

“…The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface…”
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PD/SOI SRAM performance in presence of gate-to-body tunneling current by Joshi, R.V., Ching-Te Chuang, Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.

“…This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is…”
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Effect of floating-body charge on SOI MOSFET design by Wei, A., Sherony, M.J., Antoniadis, D.A.

“…This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device…”
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Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry by Voldman, S., Hui, D., Young, D., Williams, R., Dreps, D., Howard, J., Sherony, M., Assaderaghi, F., Shahidi, G.

“…Active clamp circuits are essential to minimize electrical overshoot and undershoot and minimize reflected signals and achieve performance objectives and…”
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Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits by Zamdmer, N., Plouchart, J.-O., Kim, J., Lu, L.-H., Narasimha, S., O'Neil, P., Ray, A., Sherony, M., Wagner, L.

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Self-Annealing Effect of Tensile Liner on Thick-Tinv PMOS by Qintao Zhang, Jie Chen, Sherony, M. J.

“…Various techniques have been applied in modern CMOS technology to passivate interface traps, thus improving digital performance and reliability. Although these…”
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Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI by KAWANAKA, S, KETCHEN, M. B, NII, H, HARIFUCHI, H, SUDO, G, RAUSCH, W, KIMURA, H, NAKAO, T, PARK, H, OH, S.-H, WAITE, A, WOMACK, S, BHUSHAN, M, NARASIMHA, S, MOCUTA, A. C, AJMERA, A, LI, Y, MALIK, R, KOHYAMA, Y, CHEEK, J, YANG, I, CLARK, W. F, DIVAKARUNI, R, PEARSON, D. J, BHASIN, R, MCSTAY, K, SHERONY, M, FISHER, P, MATSUMOTO, K, UTOMO, H

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32nm general purpose bulk CMOS technology for high performance applications at low voltage by Arnaud, F., Liu, J., Lee, Y.M., Lim, K.Y., Kohler, S., Chen, J., Moon, B.K., Lai, C.W., Lipinski, M., Sang, L., Guarin, F., Hobbs, C., Ferreira, P., Ohuchi, K., Li, J., Zhuang, H., Mora, P., Zhang, Q., Nair, D.R., Lee, D.H., Chan, K.K., Satadru, S., Yang, S., Koshy, J., Hayter, W., Zaleski, M., Coolbaugh, D.V., Kim, H.W., Ee, Y.C., Sudijono, J., Thean, A., Sherony, M., Samavedam, S., Khare, M., Goldberg, C., Steegen, A.

“…This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with…”
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Transient behavior of the kink effect in partially-depleted SOI MOSFET's by Wei, A., Sherony, M.J., Antoniadis, D.A.

“…The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L/sub eff/=0.2 μm is examined as a function of drain bias, gate…”
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Advanced multi-high-operation-voltage I/O device design for 32nm gate-first HiK MG technology by Xusheng Wu, Hu, Y, Kusunoki, N, Yang, Z J, Yang, G, Teh, Y, Kirshnan, R, Krishnan, S, Shepard, J, Han, S, Lee, Y, Arnaud, F, Sherony, M, Sudijono, J, Steegen, A

“…This paper presents the advanced I/O device design for 32 nm Hi-K Metal Gate technology with multi-high operation voltages. Process optimization work is done…”
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Reduction of threshold voltage sensitivity in SOI MOSFET's by Sherony, M.J., Su, L.T., Chung, J.E., Antoniadis, D.A.

“…The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device…”
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A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process by Chen, X., Samavedam, S., Narayanan, V., Stein, K., Hobbs, C., Baiocco, C., Li, W., Jaeger, D., Zaleski, M., Yang, H. S., Kim, N., Lee, Y., Zhang, D., Kang, L., Chen, J., Zhuang, H., Sheikh, A., Wallner, J., Aquilino, M., Han, J., Jin, Z., Li, J., Massey, G., Kalpat, S., Jha, R., Moumen, N., Mo, R., Kirshnan, S., Wang, X., Chudzik, M., Chowdhury, M., Nair, D., Reddy, C., Teh, Y. W., Kothandaraman, C., Coolbaugh, D., Pandey, S., Tekleab, D., Thean, A., Sherony, M., Lage, C., Sudijono, J., Lindsay, R., Ku, J. H., Khare, M., Steegen, A.

“…For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and…”
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Performance elements for 28nm gate length bulk devices with gate first high-k metal gate by Yuan, J, Gruensfelder, C, Lim, K Y, Wallner, T, Jung, M K, Sherony, M J, Lee, Y M, Chen, J, Lai, C W, Chow, Y T, Stein, K, Song, L Y, Onoda, H, An, C W, Wang, H, Moon, B K, Kim, J, Inokuma, H, Yamasaki, H, Shah, J, Meer, H V, Samavedam, S B, Zhang, Q T, Zhu, C, Park, Y, Lim, Y E, Nieuwenhuizen, R, Han, J P, Hamaguchi, M, Lai, W L, Belyansky, M P, Gluschenkov, O, Johnson, S, Divakaruni, R, Kaste, E F, Sudijono, J, Ku, J H, Matsuoka, F, Neumueller, W, Sampson, R, Sekine, M, Steegen, A

“…In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance…”
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A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology by PLOUCHART, Jean-Olivier, KIM, Jonghae, WAGNER, Lawrence F, ZAMDMER, Noah, LU, Liang-Hung, SHERONY, Melanie, YUE TAN, GROVES, Robert A, TRZCINSKI, Robert, TALBI, Mohamed, RAY, Asit

“…This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12- mu m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass…”
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Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM by Joshi, R.V., Chuang, C.T., Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.

“…The gate tunneling current for gate oxide thickness around 2.0 nm or below has been known to increase device leakage and power dissipation, and deteriorate…”
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Process and local layout effect interaction on a high performance planar 20nm CMOS by Sato, F., Ramachandran, R., Van Meer, H., Cho, K. H., Ozbek, A., Yang, X., Liu, Y., Li, Z., Wu, X., Jain, S., Utomo, H., Kwon, U., Park, Y., Tan, W. L., Dai, X., Lai, W., Kim, J., Jones, D., Ganz, M., Bae, D. H., Lallement, R., Vemula, S. C., Kwon, T., Lee, P., Qi, Y., Weybright, M., Scholze, A., Bingert, R., King, J., Sherony, M., Eller, M., Shang, H., Tabakman, K., Narayanan, V., Samavedam, S., Divakaruni, R.

“…As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that…”
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Optimization of series resistance in sub-0.2 μm SOI MOSFET's by Su, L.T., Sherony, M.J., Hang Hu, Chung, J.E., Antoniadis, D.A.

“…The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. The series resistance…”
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Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry by Voldman, S., Hui, D., Young, D., Williams, R., Dreps, D., Howard, J., Sherony, M., Assaderaghi, F., Shahidi, G.

“…Active clamp circuits are key to minimize electrical overshoot and undershoot and minimize reflected signals and achieve performance objectives and reliability…”
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PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology by Song, L., Liang, Y., Onoda, H., Lai, C. W., Wallner, T. A., Pofelski, A., Gruensfelder, C., Josse, E., Okawa, T., Brown, J., Williams, R. Q., Holt, J., Weijtmans, J. W., Greene, B., Utomo, H. K., Lee, S. C., Nair, D., Zhang, Q., Zhu, C., Wu, X., Sherony, M., Lee, Y. M., Henson, W. K., Divakaruni, R., Kaste, E.

“…The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device,…”
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