Interconnect parasitic extraction in the digital IC design methodology

Interconnect parasitic extraction in the digital IC design methodology

Accurate interconnect analysis has become essential not only for post-layout verification but also for synthesis. This tutorial explores interconnect analysis and extraction methodology on three levels: coarse extraction to guide synthesis, detailed extraction for full-chip analysis, and full 3D ana...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design pp. 223 - 231
Main Authors: Kamon, Mattan, McCormick, Steve, Sheperd, Ken
Format: Conference Proceeding
Language:English
Published: Piscataway, NJ, USA IEEE Press 07-11-1999
Series:ACM Conferences
Subjects:
Applied computing > Physical sciences and engineering > Engineering
Computer systems organization > Architectures > Parallel architectures > Interconnection architectures
Hardware > Emerging technologies
Hardware > Integrated circuits > Interconnect
Hardware > Robustness
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Accurate interconnect analysis has become essential not only for post-layout verification but also for synthesis. This tutorial explores interconnect analysis and extraction methodology on three levels: coarse extraction to guide synthesis, detailed extraction for full-chip analysis, and full 3D analysis for critical nets. We will also describe the electrical issues caused by parasitics and how they have, and will be, influenced by changing technology. The importance of model order reduction will be described as well as methodologies at the synthesis stage for avoiding parasitic problems.
ISBN:9780780358324
0780358325
DOI:10.5555/339492.339643