Search Results - "Shen, William Wu"

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  1. 1

    Invited talks by Wu-Tung Cheng, Shen, William Wu

    Published in 2013 22nd Asian Test Symposium (01-11-2013)
    “…Provides an abstract for each of the invited presentations and a brief professional biography of each presenter. The complete presentations were not made…”
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    Conference Proceeding
  2. 2

    A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application by Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok

    Published in IEEE journal of solid-state circuits (01-04-2014)
    “…A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology…”
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    Journal Article
  3. 3

    An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application by Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok

    Published in 2013 Symposium on VLSI Technology (01-06-2013)
    “…A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on…”
    Get full text
    Conference Proceeding
  4. 4

    An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application by Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok

    Published in 2013 Symposium on VLSI Circuits (01-06-2013)
    “…A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on…”
    Get full text
    Conference Proceeding