Search Results - "Sharan, Neha"

A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry by Sharan, Neha, Mahapatra, Santanu

“…Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper,…”
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Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies by Rawat, Amita, Sharan, Neha, Jang, Doyoung, Chiarella, Thomas, Bufler, Fabian M., Catthoor, Francky, Parvais, Bertrand, Ganguly, Udayan

“…We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework-enabling the estimation of performance…”
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Continuity equation based nonquasi-static charge model for independent double gate MOSFET by Sharan, Neha, Mahapatra, Santanu

“…Using the numerical device simulation we show that the relationship between the surface potentials along the channel in any double gate (DG) MOSFET remains…”
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Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry by Sharan, Neha, Mahapatra, Santanu

“…We present a physics-based closed form small signal Nonquasi-static (NQS) model for a long channel Common Double Gate MOSFET (CDG) by taking into account the…”
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Ge Devices: A Potential Candidate for Sub-5-nm Nodes? by Sharan, Neha, Eneman, Geert, Collaert, Nadine, Parvais, Bertrand, Spessot, Alessio, Mocuta, Anda, Shaik, Khaja A., Jang, Doyoung, Schuddinck, Pieter, Yakimets, Dmitry, Bardon, Marie Garcia, Mitard, Jerome, Arimura, Hiroaki, Bufler, Fabian M.

“…In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS)…”
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Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry by Sharan, N., Mahapatra, S.

“…With the unique quasi-linear relationship between the surface potentials along the channel, recently we have proposed a quasi-static terminal charge model for…”
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Reliable techniques of leakage current reduction for SRAM-6T Cell: A review by Chauhan, Ankita, Chauhan, D. S., Sharan, Neha

“…Feature size of the transistor is shrinking by the rapid progress in semiconductor technology in deep sub-micron (DSM) technology. At the present time; these…”
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indDG: A new compact model for common double gate MOSFET adapted to gate oxide thickness asymmetry by Kumar, Chethan, Sharan, Neha, Mahapatra, Santanu

“…Here, we present a surface potential based compact model for common double gate MOSFET (indDG) along with implementation results. The model includes core…”
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Characterization of 6T CMOS SRAM in 90nm technology for various leakage reduction techniques by Chauhan, Ankita, Chauhan, D. S., Sharan, Neha

“…As the scale down the feature size of transistor, leakage power maximizes inversely. In present day's power dissipation is important factor .One of the major…”
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Cost Effective FinFET Platform for Stand Alone DRAM 1Y and Beyond Memory Periphery by Spessot, Alessio, Sharan, Neha, Oh, Hyungrock, Ritzenthaler, Romain, Litta, Eugenio Dentoni, O'Sullivan, Barry, Mallik, Arindam, De Keersgieter, An, Parvais, Bertrand, Sherazi, Yasser, Machkaoutsan, Vladimir, Kim, Cheolgyu, Fazan, Pierre, Mocuta, Dan, Mocuta, Anda, Horiguchi, Naoto

“…A new platform for Memory periphery device based on FinFET technology is proposed, targeting DRAM technology node 1Y and beyond. Up to 30% power saving is…”
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