Search Results - "Shappir, A."

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices by Lusky, E., Shacham-Diamand, Y., Mitenberg, G., Shappir, A., Bloom, I., Eitan, B.

“…A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of…”
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Highly scalable 90nm STI bounded twin flash cell with local interconnect by Nagel, N., Olligs, D., Polei, V., Parascandola, S., Boubekeur, H., Bach, L., Muller, T., Strassburg, M., Riedel, S., Kratzert, P., Caspary, D., Deppe, J., Wilier, J., Schulze, N., Mikolajick, T., Kusters, K.-H., Shappir, A., Redmard, E., Bloom, I., Eitan, B.

“…A 90nm Twin Flash memory cell with a size of 0.029/spl mu/m/sup 2//bit (3.5F/sup 2/) is presented. This cell is introduced first in a 1.8V, 2Gbit data flash…”
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Traps spectroscopy of the Si3Ni4 layer using localized charge-trapping nonvolatile memory device by Lusky, Eli, Shacham-Diamand, Yosi, Shappir, Assaf, Bloom, Ilan, Eitan, Boaz

“…A spectroscopy method is proposed and implemented for Si3Ni4 layer using the NROM® cell and the gate-induced-drain-leakage measurement. The proposed method…”
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Spatial characterization of localized charge trapping and charge redistribution in the NROM device by Shappir, Assaf, Levy, David, Shacham-Diamand, Yosi, Lusky, Eli, Bloom, Ilan, Eitan, Boaz

“…This paper discusses the spatial characterization and redistribution of hot carriers injected into the gate dielectric stack of the NROM localized charge…”
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Lateral charge transport in the nitride layer of the NROM non-volatile memory device by Shappir, Assaf, Shacham-Diamand, Yosi, Lusky, Eli, Bloom, Ilan, Eitan, Boaz

“…NROM is a two bits per cell, localized charge trapping non-volatile memory device. A unique erase state threshold voltage drift in the NROM cell is presented…”
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Relaxation of localized charge in trapping-based nonvolatile memory devices by Janai, M., Shappir, A., Bloom, I., Eitan, B.

“…Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster…”
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Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices by Shappir, Assaf, Shacham-Diamand, Yosi, Lusky, Eli, Bloom, Ilan, Eitan, Boaz

“…An analytical model is presented for the subthreshold slope degradation of localized-charge-trapping based non-volatile memory devices. The model incorporates…”
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Spatial characterization of hot carriers injected into the gate dielectric stack of a MOSFET based non-volatile memory device by Shappir, A., Levy, D., Geva, G., Shacham-Diamand, Y., Lusky, E., Bloom, I., Eitan, B.

“…Subthreshold slope degradation in the NROM/spl trade/ localized-charge-trapping non-volatile memory device is utilized to investigate the spatial distributions…”
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Data retention reliability model of NROM nonvolatile memory products by Janai, M., Eitan, B., Shappir, A., Lusky, E., Bloom, I., Cohen, G.

“…Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a…”
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The two-bit NROM reliability by Shappir, A., Lusky, E., Cohen, G., Bloom, I., Janai, M., Eitan, B.

“…Saifun NROM/spl trade/ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM…”
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Retention loss characteristics of localized charge-trapping devices by Lusky, E., Shacham-Diamand, Y., Shappir, A., Bloom, I., Cohen, G., Eitan, B.

“…NROM/sup /spl reg// is a localized charge trapping memory device that realizes two physical bits per cell. A lateral charge redistribution-based retention loss…”
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NROM Window Sensing for 2 and 4-bits per cell Products by Shappir, A., Litsky, E., Cohen, G., Eitan, B.

“…The NROM nonvolatile memory device (Eitan et al., 2000) is a unique localized charge trapping based technology, which is vastly being adopted by the industry,…”
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Charge Loss Mechanisms in a Localized Trapping Based Nonvolatile Memory Device by Yael Shur, Shacham-Diamand, Y., Lusky, E., Eitair, B., Shappir, A.

“…In this work, quantification of the theories and models attributed to the NROM cell V t decay and the dominant charge loss mechanism dictating this phenomenon…”
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4-bit per cell NROM reliability by Eitan, B., Cohen, G., Shappir, A., Eli Lusky, Givant, A., Janai, M., Bloom, I., Polansky, Y., Dadashev, O., Lavan, A., Sahar, R., Maayan, E.

“…The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required…”
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A New Twin Flash™ Cell for 2 and 4 Bit Operation at 63nm Feature Size by Nagel, N., Boubekeur, H., Heinrichsdorff, F., Bach, L., Polei, V., Gupta, J., Pritchard, D., Riedel, S., Strassburg, M., Deppe, J., Bewersdorff-Sarlette, U., Muller, T., Verhoeven, M., Lattard, L., Markert, M., Ruttkowski, E., Mikalo, R., Willer, J., Schulze, N., Ludwig, C., v. Kamienski, E.G. Stein, Mikolajick, T., Isler, M., Kusters, K.-H., Shappir, A., Shur, Y., Lusky, E., Eitan, B., Pissors, V., Sachse, J.-U., Manger, D., Caspary, D., Parascandola, S., Olligs, D.

“…A 63nm Twin Flash memory cell with a size of 0.0225μm 2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To…”
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