Search Results - "Shanbhag, Naresh"

Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection by Kim, Hyungyo, Shanbhag, Naresh R.

“…This paper presents a statistical signal processing-based algorithmic approach to enhance the compute signal-to-noise ratio (compute SNR) of 6T SRAM-based…”
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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array by Mingu Kang, Gonugondla, Sujan K., Patil, Ameya, Shanbhag, Naresh R.

“…A multi-functional in-memory inference processor integrated circuit (IC) in a 65-nm CMOS process is presented. The prototype employs a deep in-memory…”
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A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training by Gonugondla, Sujan K., Kang, Mingu, Shanbhag, Naresh R.

“…This paper presents a robust deep in-memory machine learning classifier with a stochastic gradient descent (SGD)-based on-chip trainer using a standard 16-kB…”
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Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures by Sakr, Charbel, Shanbhag, Naresh R.

“…This paper presents signal processing methods to enhance the energy vs. accuracy trade-off of in-memory computing (IMC) architectures. First, an optimal…”
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Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing by Kang, Mingu, Gonugondla, Sujan K., Shanbhag, Naresh R.

“…This article provides an overview of recently proposed deep in-memory architectures (DIMAs) in SRAM for energy- and latency-efficient hardware realization of…”
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A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting by Dbouk, Hassan, Gonugondla, Sujan K., Sakr, Charbel, Shanbhag, Naresh R.

“…This article presents a deep learning-based classifier IC for keyword spotting (KWS) in 65-nm CMOS designed using an algorithm-hardware co-design approach…”
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Binodal, wireless epidermal electronic systems with in-sensor analytics for neonatal intensive care by Chung, Ha Uk, Kim, Bong Hoon, Lee, Jong Yoon, Lee, Jungyup, Xie, Zhaoqian, Ibler, Erin M, Lee, KunHyuck, Banks, Anthony, Jeong, Ji Yoon, Kim, Jongwon, Ogle, Christopher, Grande, Dominic, Yu, Yongjoon, Jang, Hokyung, Assem, Pourya, Ryu, Dennis, Kwak, Jean Won, Namkoong, Myeong, Park, Jun Bin, Lee, Yechan, Kim, Do Hoon, Ryu, Arin, Jeong, Jaeseok, You, Kevin, Ji, Bowen, Liu, Zhuangjian, Huo, Qingze, Feng, Xue, Deng, Yujun, Xu, Yeshou, Jang, Kyung-In, Kim, Jeonghyun, Zhang, Yihui, Ghaffari, Roozbeh, Rand, Casey M, Schau, Molly, Hamvas, Aaron, Weese-Mayer, Debra E, Huang, Yonggang, Lee, Seung Min, Lee, Chi Hwan, Shanbhag, Naresh R, Paller, Amy S, Xu, Shuai, Rogers, John A

“…Existing vital sign monitoring systems in the neonatal intensive care unit (NICU) require multiple wires connected to rigid sensors with strongly adherent…”
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Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications by Gonugondla, Sujan K., Sakr, Charbel, Dbouk, Hassan, Shanbhag, Naresh R.

“…This article obtains fundamental limits on the computational precision of in-memory computing architectures (IMCs). An IMC noise model and associated…”
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Deep In-Memory Architectures for Machine Learning-Accuracy Versus Efficiency Trade-Offs by Kang, Mingu, Kim, Yongjune, Patil, Ameya D., Shanbhag, Naresh R.

“…In-memory architectures, in particular, the deep in-memory architecture (DIMA) has emerged as an attractive alternative to the traditional von Neumann…”
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Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition by Sai Zhang, Shanbhag, Naresh R.

“…Low overhead error-resiliency techniques such as algorithmic noise-tolerance (ANT) have been shown to be particularly effective for signal processing and…”
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An In-Memory VLSI Architecture for Convolutional Neural Networks by Kang, Mingu, Lim, Sungmin, Gonugondla, Sujan, Shanbhag, Naresh R.

“…This paper presents an energy-efficient and high throughput architecture for convolutional neural networks (CNN). Architectural and circuit techniques are…”
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Efficient Local Secret Sharing for Distributed Blockchain Systems by Kim, Yongjune, Raman, Ravi Kiran, Kim, Young-Sik, Varshney, Lav R., Shanbhag, Naresh R.

“…Blockchain systems store transaction data in the form of a distributed ledger where each peer is to maintain an identical copy. Blockchain systems resemble…”
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Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers by Wadhwa, Aseem, Madhow, Upamanyu, Shanbhag, Naresh R.

“…The scaling of analog-to-digital converter (ADC) power consumption with communication bandwidth imposes severe limits on its precision, which significantly…”
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Shannon-Inspired Statistical Computing for the Nanoscale Era by Shanbhag, Naresh R., Verma, Naveen, Kim, Yongjune, Patil, Ameya D., Varshney, Lav R.

“…Modern day computing systems are based on the von Neumann architecture proposed in 1945 but face dual challenges of: 1) unique data-centric requirements of…”
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An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation by Abdallah, Rami A., Shanbhag, Naresh R.

“…A subthreshold ECG processor in 45-nm IBM SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is…”
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In-Memory Computing Architectures for Sparse Distributed Memory by Mingu Kang, Shanbhag, Naresh R.

“…This paper presents an energy-efficient and high-throughput architecture for Sparse Distributed Memory (SDM)-a computational model of the human brain [1]. The…”
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Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs by Kim, Yongjune, Kang, Mingu, Varshney, Lav R., Shanbhag, Naresh R.

“…Conventional low-power static random access memories (SRAMs) reduce read energy by decreasing the bit-line voltage swings uniformly across the bit-line…”
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Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures by Roy, Saion K., Shanbhag, Naresh R.

“…Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to…”
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IMPQ: Reduced Complexity Neural Networks Via Granular Precision Assignment by Gonugondla, Sujan Kumar, Shanbhag, Naresh R.

“…The demand for the deployment of deep neural networks (DNN) on resource-constrained Edge platforms is ever increasing. Today's DNN accelerators support…”
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Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing by Ou, Han-Mo, Shanbhag, Naresh R.

“…Analog in-memory computing architectures (IMCs) have exhibited high energy efficiency over conventional digital architectures. The use of resistive memory…”
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