Search Results - "Seva, Ramu"

Energy-Performance Scalability Analysis of a Novel Quasi-Stochastic Computing Approach by Metku, Prashanthi, Seva, Ramu, Choi, Minsu

“…Stochastic computing (SC) is an emerging low-cost computation paradigm for efficient approximation. It processes data in forms of probabilities and offers…”
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An On-Chip Detector of Transient Stress Events by Patnaik, Abhishek, Beetner, Daryl G., Suchak, Mihir, Seva, Ramu, Pamidimukkala, Keerthana, Edgington, Greg, Moseley, Richard, Feddeler, James, Stockinger, Michael, Pommerenke, David

“…Testing and debugging of electrostatic discharge (ESD) or electrical fast transient issues in modern electronic systems can be challenging. The following paper…”
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Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing by Seva, Ramu, Metku, Prashanthi, Choi, Minsu

“…The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent…”
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Novel Approaches for Efficient Stochastic Computing by Seva, Ramu

“…This thesis is comprised of two papers, where the first paper presents a novel approach for parallel implementation of SC using FPGA (Field Programmable Gate…”
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Low-power null convention logic design based on modified gate diffusion input technique by Metku, Prashanthi, Seva, Ramu, Kim, Kyung Ki, Kim, Yong-Bin, Choi, Minsu

“…Null Convention Logic (NCL) is the one of the well-known clock-less approaches for designing asynchronous logic circuits. The complementary metal oxide…”
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Variable bit truncation technique for approximate stochastic computing (ASC) by Seva, Ramu, Metku, Prashanthi, Kim, Kyung Ki, Kim, Yong-Bin, Choi, Minsu

“…Lately, stochastic computing (SC) has been found to be significantly advantageous in image processing applications because of its lower hardware complexity and…”
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Approximate stochastic computing (ASC) for image processing applications by Seva, Ramu, Metku, Prashanthi, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi

“…SC (stochastic computation) has been found to be very advantageous in image processing applications because of its lower area consumption and low-power…”
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Parallel decoding for multi-stage BCH decoder by Metku, Prashanthi, Seva, Ramu, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi

“…3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive…”
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Hybrid GDI-NCL for area/power reduction by Metku, Prashanthi, Seva, Ramu, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi

“…Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead…”
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Multi-stage BCH decoder to mitigate hotspot-induced bit error variation by Metku, Prashanthi, Seva, Ramu, Kyung Ki Kim, Minsu Choi

“…3D heterogeneous integration (commonly termed as 3DIC) of CPU, GPU and DRAM dies vertically interconnected by a massive number of TSVs (Through-Silicon Vias)…”
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