Search Results - "Seto, Kenshu"

Scalar replacement in the presence of multiple write accesses for high-level synthesis by Seto, Kenshu

“…High-level synthesis (HLS) reduces design time of domain-specific accelerators from loop nests. Usually, naive usage of HLS leads to accelerators with…”
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Protocol Transducer Synthesis using Divide and Conquer approach by Watanabe, S., Seto, K., Ishikawa, Y., Komatsu, S., Fujita, M.

“…One of the efficient design methodologies for large scale system on a chip (SoC) is IP-based design. In this methodology, a system is considered as a set of…”
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Small Memory Footprint Neural Network Accelerators by Seto, Kenshu, Nejatollahi, Hamid, An, Jiyoung, Kang, Sujin, Dutt, Nikil

“…Deep Neural Network (DNN) accelerators provide high-accuracy data recognition that are commonly used in edge devices. However, resource constrained edge…”
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Custom Instruction Generation with High-Level Synthesis by Seto, K., Fujita, M.

“…This paper presents a novel approach for automatic custom instruction set generation with high-level synthesis techniques. Unlike previous approaches which…”
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SAT-based resource binding for reducing critical path delays by Seto, K., Nonaka, Y., Maruizumi, T., Shiraki, Y.

“…In this paper, a new function unit binding approach based on SAT is proposed. Differently from previous approaches, which heuristically minimize the total…”
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Dynamically reconfigurable protocol transducer by Watanabe, S., Ishikawa, Y., Seto, K., Komatsu, S., Fujita, M.

“…Protocol transducer synthesis is one of the most significant issues for efficient IP core reuse in SoC design. The authors proposed automatic protocol…”
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Pipeline scheduling for array based reconfigurable architectures considering interconnect delays by Gao, S., Seto, K., Komatsu, S., Fujita, M.

“…Pipelining is a powerful technique to achieve high performance design. Nowadays, in deep-submicron (DSM) process era, interconnect delay is becoming so…”
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Field modifiable architecture with FPGAs and its design methodology by Komatsu, S., Kojima, Y., Saito, H., Seto, K., Fujita, M.

“…In the age of highly integrated system LSIs, the problem of design methodologies with short time-to-market and higher re-programmability after the chip…”
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