Search Results - "Ser Choong, Chong"

Microelectrode Array Biochip:  Tool for In Vitro Drug Screening Based on the Detection of a Drug Effect on Dopamine Release from PC12 Cells by Cui, Hui-Fang, Ye, Jian-Shan, Chen, Yu, Chong, Ser-Choong, Sheu, Fwu-Shan

“…Novel, yet simple detection techniques of drug effect, including the effect of a vesicular monoamine transporter inhibitor (reserpine), a dopamine precursor…”
Get full text

Development of a Cu/Low- k Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications by Xiaowu Zhang, Lau, J H, Premachandran, C S, Ser-Choong Chong, Leong Ching Wai, Lee, V, Chai, T C, Kripesh, V, Sekhar, V N, Pinjala, D, Che, F X

“…Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips…”
Get full text

Significantly retarded interfacial reaction between an electroless Ni–W–P metallization and lead-free Sn–3.5Ag solder by Yang, Ying, Balaraju, J.N., Chong, Ser Choong, Xu, Hui, Liu, Changqing, Silberschmidt, Vadim V., Chen, Zhong

“…► A ternary Ni–W–P alloy has been plated as the metallization for lead-free soldering. ► The reaction mechanism and kinetics between the alloy and Sn–3.5Ag…”
Get full text

3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond by Kim, Do-Won, Yu, Li Hong, Chang, Ka Fai, Woon Leng, Loh, Ser Choong, Chong, Hong, Cai, Bhattacharya, Surya

“…In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated…”
Get full text

Ultra-Thin FO Package-on-Package for Mobile Application by Hsiao, Hsiang-Yao, Ho, Soon Wee, Lim, Simon Siak Boon, Wai, Leong Ching, Chong, Ser Choong, Sharon Lim, Pei Siang, Han, Yong, Chai, Tai Chong

“…Today, Package on Package is a major trend of three-dimensional fabrication for processors and high-performance memory applications in portable applications…”
Get full text

Fast Location of Opens in TSV-Based 3-D Chip Using Simple Resistor Chain by Sanming Hu, Cheng Jin, Hongyu Li, Rui Li, Ser Choong Chong, Ming Chinq Jong, Wai, Eva Leong Ching, Keng Hwa Teo, Minkyu Je, Lo, Patrick Guo Qiang

“…This brief proposes an electrical method using simple resistor chain in parallel to quickly locate open circuits in a 3-D chip. This method is theoretically…”
Get full text

Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip-Embedded Wafer Level Packages by Ho Siow Ling, Bu Lin, Chong Ser Choong, Velez, Sorono Dexter, Chai Tai Chong, Xiaowu Zhang

“…Comprehensive numerical and experimental analyses were performed to investigate the issue of die shift during the 12-in wafer level molding process of…”
Get full text

Heterogeneous Three-Layer TSV Chip Stacking Assembly With Moldable Underfill by Pei-Siang, Sharon Lim, Fa Xing Che, Chong Ser Choong, Rong, Michelle Chew Bi, Sekhar, Vasarla Nagendra, Rao, Vempati Srinivasa, Chai Tai Chong

“…This paper reports the study of 3-D die stacking of three chips through-silicon-via (TSV) interconnections. Two different reflow approaches were used for the…”
Get full text

Fabrication of patterned and non-patterned metallic nanowire arrays on silicon substrate by Sharma, Gaurav, Chong, Ser Choong, Ebin, Liao, Hui, Cai, Gan, Chee Lip, Kripesh, Vaidyanathan

“…Patterned micropads, 50 micrometer (μm) in diameter, comprising of multiple metallic nanowires are fabricated directly on a silicon substrate. Nanoporous…”
Get full text

Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device by Premachandran, C. S., Chong, Ser Choong, Liw, Saxon, Nagarajan, Ranganathan

“…A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded…”
Get full text

In situ temporal detection of dopamine exocytosis from l-dopa-incubated MN9D cells using microelectrode array-integrated biochip by Cui, Hui-Fang, Ye, Jian-Shan, Chen, Yu, Chong, Ser-Choong, Liu, Xiao, Lim, Tit-Meng, Sheu, Fwu-Shan

“…Dopamine (DA) is an important neurotransmitter, playing a very important role in many neurological disorders. A microelectrode array-integrated biochip has…”
Get full text

Efficient and Adaptive Semantic Segmentation of HBMs using Incremental Learning by Chang, Richard, Thakur, Namrata, Wang, Jie, Li, Yurni, Chong, Ser Choong, Singh Pahwa, Ramanpreet

“…Due to the increasing miniaturization of package interconnects, detecting multiple defects in buried structures is becoming more important and challenging…”
Get full text

Development of Flip-Chip Packaging for Monolithic Microwave Integrated Circuit by Wai, Leong Ching, Guan Lim, Teck, Chong, Ser Choong, Zhou, Lin

“…In this paper, the flip chip joints formed by using gold (Au) stud on commercial-off-the shelf (COTS) monolithic microwave integrate circuit (MMIC) designed…”
Get full text

Development of Chip to Wafer Assembly with CuSnAg Microbump on Solder on Pad Interposer using Thermocompression and Solder Reflow by Keng Yuen, Jason Au, Chong, Ser Choong, Daniel, Ismael Cereno

“…Chip to wafer (C2W) bonding to form interconnect is not new to the industry. However, if the bottom wafer has thick (i,e ≥ 10um) Cu RDL layers, the CTE…”
Get full text

Development of a Disposable Bio-Microfluidic Package With Reagents Self-Contained Reservoirs and Micro-Valves for a DNA Lab-on-a-Chip (LOC) Application by Ling Xie, Premachandran, C.S., Chew, M., Ser Choong Chong

“…A disposable self-contained microfluidic package has been developed and tested for on-chip DNA extraction from human blood for practical lab-on-a-chip…”
Get full text

Cu Damascene Process on Temporary Bonded Wafers for Thin Chip Stacking using Cu-Cu Hybrid Bonding by Sekhar, Vasarla Nagendra, Kumar, Mishra Dileep, Lianto, Prayudi, Chong, Ser Choong, Rao, Vempati Srinivasa

“…Hybrid bonding is one of the innovative permanent bonding technologies that form dielectric-dielectric and metal-metal bonds, respectively. Hybrid bonding is…”
Get full text

Multi-Chip Stacked Memory Module Development using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications by Sekhar, Vasarla Nagendra, Kumar, Mishra Dileep, Tippabhotla, Sasi Kumar, Rao, B. S. S. Chandra, Daniel, Ismael Cereno, Chong, Ser Choong, Rao, Vempati Srinivasa

“…The present study focuses on multi-chip stacked memory module development, and it encompasses a comprehensive overview of critical aspects, key learnings,…”
Get full text

Process Challenges in Thin Wafers Fabrication with Double Side Hybrid Bond Pads for Chip Stacking by Kumar, Mishra Dileep, Nagendra Sekhar, Vasarla, Rao, B.S.S. Chandra, Choong Chong, Ser, Rao, Vempati Srinivasa

“…3D packaging with stacked dies is widely explored as a future advanced packaging technology for applications involving high-performance computing and High…”
Get full text

Investigation of Void-free Chip-to-Chip Bonding Methods for CMOS-MEMS Compatibility by Yeo, Yi Xuan, Leong Ching Wai, Eva, Chen, Daniel Ssu-Han, Choong Chong, Ser

“…A thin bonding interface that is void-free and composed of materials with low attenuation is needed to achieve GHz bulk acoustic wave signal transmission for…”
Get full text

Reliability Assessment of 2.5D Module using Chip to Wafer Hybrid Bonding by Chong, Ser Choong, Au Keng Yuen, Jason, Sekhar, Vasarla Nagendra, Cereno Daniel, Ismael, Kumar, Mishra Dileep, Srinivasa Rao, Vempati

“…Wafer to wafer hybrid bonding has been established to form fine pitch interconnections for high density I/O applications [1], [2]. However, this approach has…”
Get full text